Patents by Inventor Gyeongmin Nam

Gyeongmin Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12001349
    Abstract: A storage device includes a memory device including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, and a controller configured to control the memory device. The controller is configured to determine data from a host as being any one of hot data, warm data and cold data, is configured to store the hot data in the first memory region, is configured to store the warm data in the second memory region, is configured to store the cold data in the third memory region, is configured to select a source block of first memory blocks included in the first memory region, is configured to select destination blocks in each of the second and third memory regions, and is configured to migrate each piece of unit data stored in the source block to one of the destination blocks according to a degree of hotness of each piece of the unit data.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: June 4, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanha Kim, Gyeongmin Nam, Seungryong Jang
  • Patent number: 12001709
    Abstract: Storage devices and an operating method of a storage controller configured to control storage devices. For example, the storage device may include a non-volatile memory and a storage controller. The non-volatile memory includes a first block and a second block, the first block including first memory cells each storing N-bit data, and the second block including second memory cells each storing M-bit data. During a read reclaim operation on the first block, the storage controller determines read hot data stored in the first block and writes the read hot data to the second block. The storage controller may select a first word line corresponding to a first page in which a number of error bits is equal to or greater than a threshold value and determine data stored in a page corresponding to a second word line adjacent to the first word line as the read hot data.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: June 4, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanha Kim, Gyeongmin Nam, Seungryong Jang
  • Patent number: 11886747
    Abstract: A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanha Kim, Gyeongmin Nam, Seungryong Jang
  • Publication number: 20230144368
    Abstract: A storage device includes a nonvolatile memory and a controller. The controller is configured to insert, into a hot list, a portion of a logical address received from a host and manage a hot hash table storing a position, at which the logical address is inserted into the hot list. The controller is further configured to search the hot hash table for the position, at which the logical address is inserted into the hot list, by using the logical address, determine an attribute of data corresponding to the logical address based on the search result, and store attribute information indicating the attribute of the data.
    Type: Application
    Filed: October 25, 2022
    Publication date: May 11, 2023
    Inventors: GYEONGMIN NAM, CHANHA KIM, SEUNGRYONG JANG
  • Publication number: 20230126807
    Abstract: A storage device includes a memory device including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, and a controller configured to control the memory device. The controller is configured to determine data from a host as being any one of hot data, warm data and cold data, is configured to store the hot data in the first memory region, is configured to store the warm data in the second memory region, is configured to store the cold data in the third memory region, is configured to select a source block of first memory blocks included in the first memory region, is configured to select destination blocks in each of the second and third memory regions, and is configured to migrate each piece of unit data stored in the source block to one of the destination blocks according to a degree of hotness of each piece of the unit data.
    Type: Application
    Filed: June 29, 2022
    Publication date: April 27, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chanha KIM, Gyeongmin NAM, Seungryong JANG
  • Publication number: 20230131466
    Abstract: A storage device includes a memory device including a first memory region, a second memory region, and a third memory region, the first memory region having a lowest bit-density relative to the second memory region and the third memory region, a second memory region having a medium bit-density relative to the first memory region and the third memory region, and a third memory region having a highest bit-density relative to the first memory region and the second memory region; and a controller configured to control the memory device The controller is configured to distribute data received from a host to the first to third memory regions based on attributes of the data, to determine a current state based on a data distribution amount for each of the first to third memory regions and a respective size of each of the first to third memory regions, and to perform an action of increasing or decreasing a size of the second memory region under the current state based on a reinforcement learning result for mitigating
    Type: Application
    Filed: June 24, 2022
    Publication date: April 27, 2023
    Inventors: Gyeongmin Nam, Chanha Kim, Seungryong Jang
  • Publication number: 20230130233
    Abstract: A method of operating a storage device, including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, includes determining a hotness of a logical address received with a write command and data to be written, from a host, based on the determined hotness being greater than a first hotness threshold, determining whether a wear level of the first memory region is greater than a wear threshold, and increasing the first hotness threshold and storing the data in the second memory region based on the wear level of the first memory region being greater than a threshold.
    Type: Application
    Filed: June 29, 2022
    Publication date: April 27, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gyeongmin NAM, Chanha KIM, Seungryong JANG
  • Publication number: 20230127449
    Abstract: A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.
    Type: Application
    Filed: May 11, 2022
    Publication date: April 27, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chanha KIM, Gyeongmin NAM, Seungryong JANG
  • Publication number: 20230127606
    Abstract: A storage device including: a memory device including memory blocks having different bit densities; and a controller, the controller including: a memory to store a logical address list including a number of recently received logical addresses and a hotness table including a hotness of each of the logical addresses in the list; and a processor to receive a write command, a latest logical address and data, to update a hotness of the latest logical address in the hotness table, to insert the latest logical address into the logical address list, and to control the memory device to program the data into one of the memory blocks depending on whether the hotness of the latest logical address exceeds a threshold value, the hotness of the latest logical address being updated based on how long ago a logical address the same as the latest logical address was received.
    Type: Application
    Filed: June 10, 2022
    Publication date: April 27, 2023
    Inventors: Gyeongmin NAM, Chanha Kim, Seungryong Jang
  • Publication number: 20230036616
    Abstract: Storage devices and an operating method of a storage controller configured to control storage devices. For example, the storage device may include a non-volatile memory and a storage controller. The non-volatile memory includes a first block and a second block, the first block including first memory cells each storing N-bit data, and the second block including second memory cells each storing M-bit data. During a read reclaim operation on the first block, the storage controller determines read hot data stored in the first block and writes the read hot data to the second block. The storage controller may select a first word line corresponding to a first page in which a number of error bits is equal to or greater than a threshold value and determine data stored in a page corresponding to a second word line adjacent to the first word line as the read hot data.
    Type: Application
    Filed: February 28, 2022
    Publication date: February 2, 2023
    Inventors: Chanha Kim, Gyeongmin Nam, Seungryong Jang
  • Publication number: 20230036841
    Abstract: Provided are a storage device, a storage controller, and an operating method of the storage controller. The storage device according to the inventive concept includes a non-volatile memory and a storage controller. The non-volatile memory includes a plurality of memory blocks, each memory block includes physical units having different retention strengths due to process variations, and the retention strengths respectively correspond to times that physical units retain data before respective reclaim operations for the physical units. The storage controller receives a write request and data from a host, selects a first physical unit based on hotness of data and retention strengths, and controls the non-volatile memory to write data to the first physical unit.
    Type: Application
    Filed: January 28, 2022
    Publication date: February 2, 2023
    Inventors: Chanha Kim, Gyeongmin Nam, Seungryong Jang