Abstract: A voltage generation circuit is provided, which includes a pumping unit generating a high voltage and a voltage regulation unit controlling the pumping unit to generate a target voltage in a first mode and controlling the pumping unit to generate a reserve voltage and generating the target voltage through down conversion of the reserve voltage in a second mode.

Abstract: A block decoder including a first selection unit configured to receive a block address signal and output a block select signal to any one of a plurality of blocks, and a second selection unit configured to receive a high voltage and control a potential level of the block select signal according to the block address signal.

Abstract: A voltage generator of a nonvolatile memory device includes a pump circuit for generating a pump output voltage by performing a pumping operation and raise or maintain the output voltage in response to a double enable signal or a single enable signal, a first regulator for comparing a first division voltage with a first reference voltage and generating the double enable signal according to a result of the comparison, a second regulator for comparing a second division voltage with a second reference voltage and outputting the voltage of the first level as a first regulation voltage, and a third regulator for comparing the second division voltage with the second reference voltage and generating the single enable signal according to a result of the comparison.

Abstract: A voltage generation circuit is provided, which includes a pumping unit generating a high voltage and a voltage regulation unit controlling the pumping unit to generate a target voltage in a first mode and controlling the pumping unit to generate a reserve voltage and generating the target voltage through down conversion of the reserve voltage in a second mode.

Abstract: A voltage regulator includes a voltage output unit configured to output an output voltage to a voltage output terminal; a first resistance divider configured to regulate a divided resistance value in response to a first series of control signals; and a second resistance divider configured to regulate the divided resistance value, which is determined in the first resistance divider, in response to a second series of control signals. A voltage level of the output voltage output through the voltage output terminal is regulated according to a ratio of the divided resistance value determined through the first resistance divider and the second resistance divider and a resistance value of a reference resistor.

Abstract: A semiconductor memory apparatus includes a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line, an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings, an erase operation determination circuit configured to generate a block erase enable signal when hot holes of at least a target number are supplied to a first channel layer of the channel layers, and a control circuit configured to perform the erase operation in response to the block erase enable signal.

Abstract: A temperature sensing circuit comprises a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation, and a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal.

Abstract: A block decoder including a first selection unit configured to receive a block address signal and output a block select signal to any one of a plurality of blocks, and a second selection unit configured to receive a high voltage and control a potential level of the block select signal according to the block address signal.

Abstract: A voltage generator of a nonvolatile memory device includes a pump circuit for generating a pump output voltage by performing a pumping operation and raise or maintain the output voltage in response to a double enable signal or a single enable signal, a first regulator for comparing a first division voltage with a first reference voltage and generating the double enable signal according to a result of the comparison, a second regulator for comparing a second division voltage with a second reference voltage and outputting the voltage of the first level as a first regulation voltage, and a third regulator for comparing the second division voltage with the second reference voltage and generating the single enable signal according to a result of the comparison.

Abstract: A semiconductor memory device includes memory blocks each comprising a plurality of memory cells formed over a semiconductor substrate having a P well, a first voltage generator supplying operating voltages to an selected block of the memory blocks, and a second voltage generator generating a negative voltage to the P well during a program operation.

Abstract: A circuit for supplying well voltages in a nonvolatile memory device includes an erase voltage supply unit for supplying an erase voltage to a well in response to an erase enable signal, a discharge unit for discharging the erase voltage, supplied to the well, in response to a discharge control signal, and a negative voltage supply unit for supplying a negative voltage to the well in response to a negative voltage output enable signal.

Abstract: A voltage regulator includes a voltage output unit configured to output an output voltage to a voltage output terminal; a first resistance divider configured to regulate a divided resistance value in response to a first series of control signals; and a second resistance divider configured to regulate the divided resistance value, which is determined in the first resistance divider, in response to a second series of control signals. A voltage level of the output voltage output through the voltage output terminal is regulated according to a ratio of the divided resistance value determined through the first resistance divider and the second resistance divider and a resistance value of a reference resistor.

Abstract: A semiconductor memory apparatus includes a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line, an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings, an erase operation determination circuit configured to generate a block erase enable signal when hot holes of at least a target number are supplied to a first channel layer of the channel layers, and a control circuit configured to perform the erase operation in response to the block erase enable signal.

Abstract: A temperature sensing circuit comprises a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation, and a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal.

Abstract: A temperature sensing circuit comprises a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation, and a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal.

Abstract: An internal voltage generating apparatus includes: a voltage detector that detects the level of the internal voltage and outputs a fixed level detection signal and a variable level detection signal. An oscillation controller generates an oscillation enable signal according to whether the fixed level detection signal and the variable level detection signal are enabled. An internal voltage generator generates the internal voltage in response to the oscillation enable signal.

Abstract: A semiconductor memory device includes memory blocks each comprising a plurality of memory cells formed over a semiconductor substrate having a P well, a first voltage generator supplying operating voltages to an selected block of the memory blocks, and a second voltage generator generating a negative voltage to the P well during a program operation.

Abstract: A circuit for supplying well voltages in a nonvolatile memory device includes an erase voltage supply unit for supplying an erase voltage to a well in response to an erase enable signal, a discharge unit for discharging the erase voltage, supplied to the well, in response to a discharge control signal, and a negative voltage supply unit for supplying a negative voltage to the well in response to a negative voltage output enable signal.

Abstract: An internal voltage generating circuit includes a voltage divider for generating a level signal by voltage-dividing first internal voltage, a pull-down signal generator for generating a pull-down signal, which has a level adjusted according to a temperature, in response to the level signal, a pull-up signal generator for generating a pull-up signal, which has a level adjusted according to the temperature, in response to the level signal, and a driving unit for driving second internal voltage in response to the pull-down signal and the pull-up signal. Driving force of the driving unit for driving the second internal voltage is changed according to the temperature.

Abstract: An apparatus for generating a power up signal for a semiconductor memory chip includes a temperature information providing unit that outputs a control voltage corresponding to predetermined temperature information. A power up signal generating unit generates the power up signal based at least on one of an external voltage or the control voltage.