Abstract: Methods and systems are described for improving a data at a receiver using one or more signal peak detectors. A signal is received having an initial signal level from the transmitter, the signal having a long bit and a short bit. The initial signal voltage of the signal is measured using a signal peak detector. A pre-emphasis value is determined using the signal voltage and is communicated to the transmitter, causing the transmitter to transmit the signal using an adjusted signal level. A second signal voltage of the initial signal is measured using a second signal peak detector, the second signal voltage being used to determine the pre-emphasis value. In another embodiment, a state machine having data relating to appropriate pre-emphasis is used in determining the pre-emphasis value. In another embodiment, one peak detector is used to measure the long bit and another peak detector is used to measure the short bit. In another embodiment, the signal does not have associated link training data.

Abstract: A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a receiver or sink device from a transmitter, the signal may be a link training signal used for configuring a link between the two devices. In the receiver, an internally generated clock signal is created, the signal having an internal frequency. The incoming signal and the internally generated clock signal are input into a frequency detector which outputs frequency comparison-based data. The internal frequency is based on the comparison-based data such that it is adjusted to be closer to the known frequency of the incoming signal.

Abstract: Methods and systems are described for enabling display system power saving during the operation of display devices. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes timing control circuitry configured to implement a power saving process during the blanking periods of the video signal. The invention further includes methods that support the operation of power saving processes.

Abstract: A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a receiver or sink device from a transmitter, the signal may be a link training signal used for configuring a link between the two devices. In the receiver, an internally generated clock signal is created, the signal having an internal frequency. The incoming signal and the internally generated clock signal are input into a frequency detector which outputs frequency comparison-based data. The internal frequency is based on the comparison-based data such that it is adjusted to be closer to the known frequency of the incoming signal.

Abstract: Methods and systems are described for improving a data at a receiver using one or more signal peak detectors. A signal is received having an initial signal level from the transmitter, the signal having a long bit and a short bit. The initial signal voltage of the signal is measured using a signal peak detector. A pre-emphasis value is determined using the signal voltage and is communicated to the transmitter, causing the transmitter to transmit the signal using an adjusted signal level. A second signal voltage of the initial signal is measured using a second signal peak detector, the second signal voltage being used to determine the pre-emphasis value. In another embodiment, a state machine having data relating to appropriate pre-emphasis is used in determining the pre-emphasis value. In another embodiment, one peak detector is used to measure the long bit and another peak detector is used to measure the short bit. In another embodiment, the signal does not have associated link training data.

Abstract: Methods and systems are described for enabling display system power saving during the operation of display devices. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes timing control circuitry configured to implement a power saving process during the blanking periods of the video signal. The invention further includes methods that support the operation of power saving processes.

Abstract: A liquid crystal display capable of testing defects of wiring in panel comprising a TFT array unit including a plurality of gate lines and data lines formed in a matrix shape, having TFT transistors at the intersection of each of the gate lines and the data lines; a data pad unit commonly connected to the plurality of data lines, for receiving signals for driving the data lines; and a wiring unit for testing defects in the data line, being connected between the data pad unit and the data line, and testing for disconnection and short anomalies of the data line.

Abstract: A liquid crystal display, comprising: a plurality of gate lines being spaced in a selected distance; a plurality of data lines being spaced in a selected distance, the data lines where a data line driving signal is provided being crossed with the gate lines to define a plurality of R, G and B pixel regions, each of data lines being split into a pair of data lines; a plurality of R, G and B dots disposed in the R, G, and B pixel regions, respectively; and a plurality of switching devices disposed in the R, G, B pixel regions, each being connected to corresponding gate line and data line of a plurality of gate lines and data lines; wherein by the split data lines, each of the R, G and B pixel regions is divided into a plurality of R, G and B sub pixel regions; and each of the R, G and B dots includes a plurality of R, G and B subdots, each of R, G and B subdots being disposed in each of R, G and B sub pixel regions, respectively.

Abstract: A liquid crystal display capable of testing defects of wiring in panel. The liquid crystal display comprising: a TFT array unit comprising a plurality of gate lines and data lines formed in a matrix shape, having TFT transistors at the intersection of the gate line and the data line; a data pad unit commonly connected to the plurality of data lines, receiving signals for driving the data lines; and a wiring unit for testing defects of data line, connected between the data pad unit and the data line, testing disconnection and short of the data line.

Abstract: A liquid crystal display having a signal line for driving gate driver IC in panel is provided. The liquid crystal display comprises: a gate driving power supply unit for supplying analog signals; a control circuit unit for applying control signal to analog signal outputted from the gate driving power supply unit; a correction circuit unit for applying control signal from the control circuit unit to correct analog signal outputted from the gate driving power supply unit into a saw type; and a corrected power supply unit for supplying saw type signals corrected in the correction circuit unit to the gate driver IC.

Abstract: Disclosed is a thin film transistor liquid crystal display having a vertical thin film transistor.

Abstract: A liquid crystal display, comprising: a plurality of gate lines being spaced in a selected distance; a plurality of data lines being spaced in a selected distance, the data lines where a data line driving signal is provided being crossed with the gate lines to define a plurality of R, G and B pixel regions, each of data lines being split into a pair of data lines; a plurality of R, G and B dots disposed in the R, G, and B pixel regions, respectively; and a plurality of switching devices disposed in the R, G, B pixel regions, each being connected to corresponding gate line and data line of a plurality of gate lines and data lines; wherein by the split data lines, each of the R, G and B pixel regions is divided into a plurality of R, G and B sub pixel regions; and each of the R, G and B dots includes a plurality of R, G and B subdots, each of R, G and B subdots being disposed in each of R, G and B sub pixel regions, respectively.

Abstract: A liquid crystal display, comprising: a plurality of gate lines being spaced in a selected distance; a plurality of data lines being spaced in a selected distance, the data lines where a data line driving signal is provided being crossed with the gate lines to define a plurality of R, G and B pixel regions, each of data lines being split into a pair of data lines; a plurality of R, G and B dots disposed in the R, G, and B pixel regions, respectively; and a plurality of switching devices disposed in the R, G, B pixel regions, each being connected to corresponding gate line and data line of a plurality of gate lines and data lines; wherein by the split data lines, each of the R, G and B pixel regions is divided into a plurality of R, G and B sub pixel regions; and each of the R, G and B dots includes a plurality of R, G and B subdots, each of R, G and B subdots being disposed in each of R, G and B sub pixel regions, respectively.

Abstract: Disclosed is a thin film transistor-liquid crystal display(TFT-LCD) having enhanced picture quality. The TFT-LCD comprises: an array substrate; a gate bus line disposed on the array substrate in a selected direction; a data bus line disposed to be crossed with the gate bus line; a pair of thin film transistors disposed at an intersection of the gate bus line and the data bus line and disposed at both sides of the data bus line respectively; a pixel electrode in contact with the respective thin film transistors; a gate insulating layer for insulating the gate bus line and the data bus line; and an intermetal insulating layer for insulating the data bus line and the pixel electrode, wherein the pair of thin film transistors have a source electrode in common.