Abstract: A semiconductor device includes a substrate having a cell area including a memory cell region and a dummy cell region, gate structures formed in the cell region, an insulating interlayer formed on the substrate to cover the gate structures, plugs formed through the insulating interlayer, bit lines contacting the plugs in the memory cell region, and dummy bit line structures contacting the plugs in the dummy cell region. The dummy bit line structure prevents a leakage current generated in a peripheral circuit area from flowing into a cell area.

Abstract: According to some embodiments of the invention, there is provided recessed transistors without semiconductor substrate fences formed on the sidewalls of a device isolation layer and methods of forming the same. The recessed transistors and methods provide a way of removing the fences of the semiconductor substrate from the sidewalls of the device isolation layer to increase the effective width of a channel region. The recessed transistors and methods include forming the device isolation layer on the semiconductor substrate to isolate an active region. Further, a channel-portion hole is formed in the active region so that the sidewall height of the channel-portion hole is greater in a width direction of the active region than in a length direction thereof. A gate pattern may further be formed across the active region such that it fills the channel-portion hole.

Abstract: A semiconductor device, including an interlayer dielectric layer having a bonding pad and a fuse on a semiconductor substrate, the interlayer dielectric layer having a pad opening and a fuse opening exposing the bonding pad and the fuse, an organic passivation layer on the interlayer dielectric layer, and a fuse passivation layer covering the organic passivation layer, a side surface of the pad opening, a side surface of the fuse opening, and a bottom surface of the fuse opening.

Abstract: According to some embodiments of the invention, there is provided recessed transistors without semiconductor substrate fences formed on the sidewalls of a device isolation layer and methods of forming the same. The recessed transistors and methods provide a way of removing the fences of the semiconductor substrate from the sidewalls of the device isolation layer to increase the effective width of a channel region. The recessed transistors and methods include forming the device isolation layer on the semiconductor substrate to isolate an active region. Further, a channel-portion hole is formed in the active region so that the sidewall height of the channel-portion hole is greater in a width direction of the active region than in a length direction thereof. A gate pattern may further be formed across the active region such that it fills the channel-portion hole.