Abstract: A semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip is provided. The semiconductor integrated circuit includes a plurality of TAP cores sharing a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of a boundary scan register circuit is connected to the test data input pin. Input ports of a selection signal generating circuit are connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. The selection signal generating circuit generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through these input pins.

Abstract: A semiconductor integrated circuit device includes a logic circuit having a plurality of observation points and a control point, a plurality of scan cells, a first multiplexer for selecting one of normal data supplied from the logic circuit or one of data supplied from the one or more observation points and outputting the selected data, and a second multiplexer for outputting one of the normal data and scan data supplied from the scan cells to the control point. A select signal for selecting outputs of the first and second multiplexers may be an output of a scan cell of the device. When test points are inserted into a scan-designed circuit, the device may use existing cells constructed therein to minimize the number of added pins. Thus, it is possible to maximally enhance testability with minimal overhead.

Abstract: Functional blocks of an integrated circuit are tested in real time using a restricted number of output pins. The apparatus of the invention comprises an integrated circuit including a plurality of functional blocks, each of which, in response to a given stimulus, generates a similar output. The apparatus includes: a comparator for comparing the levels of like output signals from each of the functional blocks and for outputting the comparison result; a transmitter for external transmission of one of the output signals in response to the comparison result; and a failure discriminator for comparing the transmitted output signal level to a predetermined target output signal level, and if similar, transmitting a positive test result signal.

Abstract: A semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip is provided. The semiconductor integrated circuit includes a plurality of TAP cores sharing a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of a boundary scan register circuit is connected to the test data input pin. Input ports of a selection signal generating circuit are connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. The selection signal generating circuit generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through these input pins.

Abstract: As system-on-a-chip (SOC) designs become popular these days, the number of embedded cores in a chip gets larger, raising test issues of glue logic test as well as embedded core test. A core-embedded integrated circuit comprising a first logic block, a second logic block, a signal line coupled between the first logic block and the second logic block for inputting/outputting an input/output signal of the logic blocks, and a boundary scan cell coupled to the signal line for loading /capturing the input/output signal for testing one or both of the first logic block and the second logic block (individually or together), with minimum overhead. Each boundary scan cell includes a data holding capability for data loading from the first and/or second logic block, wherein each boundary scan cell is adapted for serial connection with another of a plurality of like boundary scan cells (boundary scan cell chaining).

Abstract: A semiconductor integrated circuit device includes a logic circuit having a plurality of observation points and a control point, a plurality of scan cells, a first multiplexer for selecting one of normal data supplied from the logic circuit or one of data supplied from the one or more observation points and outputting the selected data, and a second multiplexer for outputting one of the normal data and scan data supplied from the scan cells to the control point. A select signal for selecting outputs of the first and second multiplexers may be an output of a scan cell of the device. When test points are inserted into a scan-designed circuit, the device may use existing cells constructed therein to minimize the number of added pins. Thus, it is possible to maximally enhance testability with minimal overhead.

Abstract: A parallel signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is counterbalanced. In an embodiment, a signature pattern from a circuit to be tested is latched, and then the latched pattern is compressed two or more times until a next signature pattern is outputted from the circuit to be test. The compression is performed by shifting the latched pattern serially by use of a multiple input signature register.

Abstract: A parallel signature compression circuit includes two or more MISRs (multiple input signature registers) coupled in series. The signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is counterbalanced. In an embodiment, a signature compression circuit has two MISRs and prevents the error masking due to the repetitive error patterns of the odd-numbered distances. In another embodiment, in order to reduce the error masking by the repetitive error patterns with even-numbered distances, the repetitive error patterns are compressed as many times as possible within the range of design rule.

Abstract: A method for testing a semiconductor device having a logic, a nonvolatile memory and a code generator for generating a code in response to the output of the nonvolatile memory is provided. The method includes the steps of loading a program, generating a code, inputting the code, testing the nonvolatile memory, comparing, checking the test response, revising the test program, and testing the semiconductor device. Specifically, the test program is loaded on the tester. Then a code is generated from memory data stored in the nonvolatile memory, and the code is input into the tester. The nonvolatile memory of the semiconductor device is tested, and the test response output from the code generator is stored in a predetermined memory of the tester. The test response is compared with the code, and the code is replaced by the test response if the test response and the code are the same with each other.