Patents by Inventor Gyorgy Suto

Gyorgy Suto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for providing rule patterns on grids
    Patent number: 9747399
    Abstract: Described is a machine-readable storage media having one or more machine executable instructions stored there on that when executed cause one or more processors to perform an operation comprising: define properties of a layout grid, wherein the layout grid provides a three dimensional (3D) space for organizing a plurality of objects on the layout grid; and define rules for the plurality of objects, wherein the rules define a relationship between the plurality of objects with reference to the defined properties of the layout grid.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Gyorgy Suto, Aaron B. Kohlmeier
  • METHOD AND APPARATUS FOR PROVIDING RULE PATTERNS ON GRIDS
    Publication number: 20170083638
    Abstract: Described is a machine-readable storage media having one or more machine executable instructions stored there on that when executed cause one or more processors to perform an operation comprising: define properties of a layout grid, wherein the layout grid provides a three dimensional (3D) space for organizing a plurality of objects on the layout grid; and define rules for the plurality of objects, wherein the rules define a relationship between the plurality of objects with reference to the defined properties of the layout grid.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Gyorgy Suto, Aaron B. Kohlmeier
  • System and method for VLSI CAD design
    Patent number: 7185304
    Abstract: A VLSI CAD system includes formulaic representations of grid lines to form grid boxes in a manner that enhances expressivity and reduces the amount of required processing resources.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Gyorgy Suto, Kartik Gopal, Carl Simonsen
  • System and method for VLSI CAD design
    Publication number: 20060085780
    Abstract: A VLSI CAD system includes formulaic representations of grid lines to form grid boxes in a manner that enhances expressivity and reduces the amount of required processing resources.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 20, 2006
    Inventors: Gyorgy Suto, Kartik Gopal, Carl Simonsen
  • Method and apparatus for detail routing using obstacle carving around terminals
    Patent number: 6957407
    Abstract: Detail routing using obstacle carving around terminals. A terminal in an integrated circuit layout object that is separated from an obstacle by less than a spacing specified by a design rule is identified. The obstacle is carved to reduce an area of the obstacle by an overlap between the obstacle and the terminal bloated by the spacing.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: October 18, 2005
    Assignee: Intel Corporation
    Inventor: Gyorgy Suto
  • Method and apparatus for detail routing using obstacle carving around terminals
    Publication number: 20030009736
    Abstract: Detail routing using obstacle carving around terminals. A terminal in an integrated circuit layout object that is separated from an obstacle by less than a spacing specified by a design rule is identified. The obstacle is carved to reduce an area of the obstacle by an overlap between the obstacle and the terminal bloated by the spacing.
    Type: Application
    Filed: July 26, 2002
    Publication date: January 9, 2003
    Inventor: Gyorgy Suto
  • Accurate layout modeling for centerline-based detail routing
    Patent number: 6480993
    Abstract: Some embodiments of the invention include a computerize method of modeling a layout for a circuit design comprising receiving a plurality of circuit elements and receiving a plurality of design rules for a layout comprising the plurality of circuit elements. The computerized method further includes generating a layout model through computer automated operations wherein one or more constraints corresponding to the design rules effective at each point in a search space of the layout model are indicated by a color associated with the point.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: November 12, 2002
    Assignee: Intel Corporation
    Inventors: Gyorgy Suto, Eric Todd
  • Method and apparatus for detail routing using obstacle carving around terminals
    Patent number: 6446246
    Abstract: Detail routing using obstacle carving around terminals. A terminal in an integrated circuit layout object that is separated from an obstacle by less than a spacing specified by a design rule is identified. The obstacle is carved to reduce an area of the obstacle by an overlap between the obstacle and the terminal bloated by the spacing.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: September 3, 2002
    Assignee: Intel Corporation
    Inventor: Gyorgy Suto