Patents by Inventor Gyosub LEE

Gyosub LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107894
    Abstract: Provided is a Group III-V compound semiconductor device. The device includes a substrate, a compound semiconductor layer provided on the substrate; and a buffer layer interposed between the compound semiconductor layer and the substrate. The compound semiconductor layer includes a first semiconductor area having a first conductivity type and a second semiconductor area having a second conductivity type. The buffer layer includes a high electron density area. In the buffer layer, an electron density of the high electron density area is higher than an electron density outside the high electron density area.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 31, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyunsu Ju, Jin-Dong Song, Joonyeon Chang, Gyosub Lee
  • Patent number: 10990542
    Abstract: The flash memory system according to the embodiment of the present invention is characterized by programming a selected page in a quantization signal generating operation, providing a reference read voltage to a selected word line connected to the selected page, A flash memory for generating a flash memory; And a memory controller for receiving a quantized signal from the flash memory and generating a response using the quantized signal, wherein the memory controller receives an challenge from a host and the flash memory performs the quantized signal generation.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 27, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyunsu Ju, Gyosub Lee
  • Patent number: 10992483
    Abstract: A physically unclonable function (PUF) device includes a memory cell array including a plurality of memory cells, a selecting circuit configured to select one or more memory cells among the plurality of memory cells in response to a challenge, and a sense amplifier and quantizer configured to generate a quantize signal from the selected memory cell. The number of quantization sections for generating the quantize signal may be different from the number of resistance state distributions generated from the selected memory cell. One or more quantization sections may exist in one resistance state distribution section.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 27, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyunsu Ju, Gyosub Lee
  • Publication number: 20200026666
    Abstract: The flash memory system according to the embodiment of the present invention is characterized by programming a selected page in a quantization signal generating operation, providing a reference read voltage to a selected word line connected to the selected page, A flash memory for generating a flash memory; And a memory controller for receiving a quantized signal from the flash memory and generating a response using the quantized signal, wherein the memory controller receives an challenge from a host and the flash memory performs the quantized signal generation.
    Type: Application
    Filed: May 29, 2019
    Publication date: January 23, 2020
    Inventors: Hyunsu JU, Gyosub LEE
  • Publication number: 20190363898
    Abstract: A physically unclonable function (PUF) device includes a memory cell array including a plurality of memory cells, a selecting circuit configured to select one or more memory cells among the plurality of memory cells in response to a challenge, and a sense amplifier and quantizer configured to generate a quantize signal from the selected memory cell. The number of quantization sections for generating the quantize signal may be different from the number of resistance state distributions generated from the selected memory cell. One or more quantization sections may exist in one resistance state distribution section.
    Type: Application
    Filed: May 28, 2019
    Publication date: November 28, 2019
    Inventors: Hyunsu JU, Gyosub LEE
  • Publication number: 20190267453
    Abstract: Provided is a Group III-V compound semiconductor device. The device includes a substrate, a compound semiconductor layer provided on the substrate; and a buffer layer interposed between the compound semiconductor layer and the substrate. The compound semiconductor layer includes a first semiconductor area having a first conductivity type and a second semiconductor area having a second conductivity type. The buffer layer includes a high electron density area. In the buffer layer, an electron density of the high electron density area is higher than an electron density outside the high electron density area.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Inventors: Hyunsu JU, Jin-Dong SONG, Joonyeon CHANG, Gyosub LEE