Patents by Inventor Gyuho KANG
Gyuho KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071899Abstract: Provided is a semiconductor package. The semiconductor package including a redistribution structure including a plurality of redistribution conductive patterns, a plurality of conductive vias connected to at least one of the plurality of redistribution conductive patterns, a plurality of lower pads connected to the plurality of conductive vias, and a plurality of redistribution insulation layers and the plurality of redistribution conductive patterns alternating each other, a semiconductor chip arranged on the redistribution structure, and an external connection terminal attached to the plurality of lower surface pads of the redistribution structure, wherein each of the plurality of redistribution conductive patterns includes a metal layer including copper and a skin layer arranged on an upper surface of the metal layer and including copper and nickel, may be provided.Type: ApplicationFiled: August 16, 2023Publication date: February 29, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Gyuho KANG, Hyungjun PARK, Seonghoon BAE, Sanghyuck OH, Kwangok JEONG, Juil CHOI
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Publication number: 20240047319Abstract: A semiconductor package includes a first substrate, a semiconductor chip on the first substrate, a second substrate spaced apart from the first substrate, a wire spaced apart from a lateral surface of the semiconductor chip and connecting the first substrate to the second substrate, a mold structure on a top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and a lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire and is between the wire and the mold structure.Type: ApplicationFiled: March 23, 2023Publication date: February 8, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongho PARK, Gyuho Kang, Sung Keun Park, Seong-Hoon Bae, Jaemok Jung, Ju-ll Choi
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Publication number: 20230282582Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Inventors: Ju-Il CHOI, Gyuho KANG, Seong-Hoon BAE, Dongjoon OH, Chungsun LEE, Hyunsu HWANG
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Publication number: 20230275011Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jeonggi Jin, Gyuho Kang, Solji Song, Un-Byoung Kang, Ju-Il Choi
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Patent number: 11742271Abstract: A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.Type: GrantFiled: May 4, 2021Date of Patent: August 29, 2023Inventors: Gyuho Kang, Seong-Hoon Bae, Jin Ho An, Teahwa Jeong, Ju-Il Choi, Atsushi Fujisaki
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Publication number: 20230260923Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.Type: ApplicationFiled: April 26, 2023Publication date: August 17, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-Il CHOI, Gyuho Kang, Un-Byoung Kang, Byeongchan Kim, Junyoung Park, Jongho Lee, Hyunsu Hwang
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Patent number: 11682630Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.Type: GrantFiled: June 16, 2021Date of Patent: June 20, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Il Choi, Gyuho Kang, Un-Byoung Kang, Byeongchan Kim, Junyoung Park, Jongho Lee, Hyunsu Hwang
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Patent number: 11676887Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.Type: GrantFiled: May 12, 2021Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeonggi Jin, Gyuho Kang, Solji Song, Un-Byoung Kang, Ju-Il Choi
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Patent number: 11664312Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.Type: GrantFiled: January 13, 2021Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Il Choi, Gyuho Kang, Seong-Hoon Bae, Dongjoon Oh, Chungsun Lee, Hyunsu Hwang
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Publication number: 20230103196Abstract: A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.Type: ApplicationFiled: May 10, 2022Publication date: March 30, 2023Inventors: GYUHO KANG, JONGHO PARK, SEONG-HOON BAE, JEONGGI JIN, JU-IL CHOI, ATSUSHI FUJISAKI
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Publication number: 20230042063Abstract: A semiconductor package includes; laterally stacked semiconductor blocks disposed side by side in a first horizontal direction on a redistribution structure, wherein each semiconductor block among the laterally stacked semiconductor blocks includes laterally stacked semiconductor chips, a heat dissipation plate, and a first molding member on the laterally stacked semiconductor chips.Type: ApplicationFiled: June 28, 2022Publication date: February 9, 2023Inventors: SEONGHOON BAE, JUIL CHOI, GYUHO KANG, JONGHO PARK, ATSUSHI FUJISAKI
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Publication number: 20230010936Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.Type: ApplicationFiled: January 4, 2022Publication date: January 12, 2023Inventors: JEONGGI JIN, GYUHO KANG, UNBYOUNG KANG, HEEWON KIM, JUMYONG PARK, HYUNSU HWANG
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Publication number: 20220399316Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.Type: ApplicationFiled: February 22, 2022Publication date: December 15, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-Il CHOI, Gyuho KANG, Heewon KIM, Sechul PARK, Jongho PARK, Junyoung PARK
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Publication number: 20220157702Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.Type: ApplicationFiled: July 21, 2021Publication date: May 19, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: JU-IL CHOI, GYUHO KANG, SEONG-HOON BAE, JIN HO AN, JEONGGI JIN, ATSUSHI FUJISAKI
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Publication number: 20220077043Abstract: A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.Type: ApplicationFiled: May 4, 2021Publication date: March 10, 2022Inventors: GYUHO KANG, SEONG-HOON BAE, JIN HO AN, TEAHWA JEONG, JU-IL CHOI, ATSUSHI FUJISAKI
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Publication number: 20220077040Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.Type: ApplicationFiled: May 12, 2021Publication date: March 10, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jeonggi JIN, Gyuho KANG, Solji SONG, Un-Byoung KANG, Ju-Il CHOI
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Publication number: 20220037261Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.Type: ApplicationFiled: June 16, 2021Publication date: February 3, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-Il CHOI, Gyuho KANG, Un-Byoung KANG, Byeongchan KIM, Junyoung PARK, Jongho LEE, Hyunsu HWANG
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Publication number: 20220020714Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.Type: ApplicationFiled: March 17, 2021Publication date: January 20, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-Il CHOI, Gyuho KANG, Heewon KIM, Junyoung PARK, Seong-Hoon BAE, Jin Ho AN
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Publication number: 20210384137Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.Type: ApplicationFiled: January 13, 2021Publication date: December 9, 2021Inventors: Ju-IL CHOI, Gyuho KANG, Seong-Hoon BAE, Dongjoon OH, Chungsun LEE, Hyunsu HWANG