Patents by Inventor Gyu-Il Cha

Gyu-Il Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190833
    Abstract: Disclosed herein is a method for moving magic states through boundary extension in a rotated surface code. The method for moving magic states includes identifying logical data and an ancilla qubit constituting a logical qubit block, and an available magic state logical qubit from a magic state storage space, identifying a type of a movement operation and a bending location during movement by analyzing a path through which the magic state logical qubit is moved to a location of a desired logical ancilla qubit, defining a movement operation process based on boundary extension in consideration of the type of the movement operation and the bending location during the movement, and moving the magic state logical qubit to the location of the logical ancilla qubit in conformity with the movement operation process.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 12, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang-Min LEE, Soo-Cheol OH, Young-Chul KIM, Chei-Yol KIM, Jin-Ho ON, Eun-Young CHO, Ki-Sung JIN, GYU-IL CHA
  • Publication number: 20250061361
    Abstract: Disclosed herein is an apparatus and method for executing a magic state distillation circuit in a logical qubit quantum system. The apparatus outputs a distilled magic state |Y>L by executing a magic state |Y>L distillation circuit in which multiple multi-target CNOT operations are performed in parallel and outputs a distilled magic state |A>L by executing a magic state |A>L distillation circuit in which multiple multi-target CNOT operations are performed in parallel. The magic state |Y>L distillation circuit is configured with three code blocks, code blocks 1 and 2 being configured with multiple multi-target CNOT operations and code block 3 being configured with SL operations and measurement operations, and the magic state |A>L distillation circuit is configured with three code blocks, code blocks 1 and 2 being configured with multiple multi-target CNOT operations and code block 3 being configured with TL+ operations and measurement operations.
    Type: Application
    Filed: August 13, 2024
    Publication date: February 20, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo-Cheol OH, Young-Chul KIM, Chei-Yol KIM, Jin-Ho ON, Sang-Min LEE, Eun-Young CHO, Ki-Sung JIN, Gyu-Il CHA
  • Publication number: 20240303523
    Abstract: Disclosed herein are an apparatus and method for performing a fault-tolerant logical Hadamard gate operation. The apparatus is configured to perform a transversal logical Hadamard (H) operation of defining a logical quantum state and logical operators of a Hadamard-transformed logical qubit on a logical qubit of a prepared encoding flavor having an arbitrary quantum state, deform a boundary of the logical qubit while maintaining the logical quantum state using a boundary deformation technology, and perform an automatic flip of transforming a flavor of the logical qubit by flipping a rotated surface code while maintaining the logical quantum state and the definition of logical operators.
    Type: Application
    Filed: November 21, 2023
    Publication date: September 12, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang-Min LEE, Young-Chul KIM, Soo-Cheol OH, Jin-Ho ON, Ki-Sung JIN, Gyu-Il CHA
  • Publication number: 20240177046
    Abstract: Disclosed herein are a quantum simulation apparatus and method using logical qubit synthesis. The quantum simulation apparatus is configured to generate a new virtual quantum device configured using magic qubits by dividing each logical qubit into multiple areas, extract logical qubit information from a target virtual quantum device that is a target of a logical Controlled NOT (CNOT) operation, synthesize the extracted logical qubit information into the new virtual quantum device, perform a logical CNOT operation in the synthesized virtual quantum device, extract logical qubit information from a result of the logical CNOT operation in the synthesized virtual quantum device, and synthesize the logical qubit information extracted from the result of the logical CNOT operation into the target virtual quantum device.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 30, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ki-Sung JIN, GYU-IL CHA
  • Publication number: 20240127094
    Abstract: Disclosed herein are a logical qubit execution apparatus and method. The logical qubit execution apparatus may be configured to execute, by a logical execution layer, a quantum circuit including requested logical qubits using a lattice surgery operation, generate, by the logical execution layer, measurement results of the logical qubits by combining measurement results of logical Pauli frames, generate, by a physical execution layer, a physical qubit circuit by converting a logical qubit operation corresponding to the measurement results of the logical qubits into a physical qubit operation, and measure, by the physical execution layer, results of an operation on physical Pauli frames by executing the physical qubit circuit.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 18, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho ON, Chei-Yol KIM, Soo-Cheol OH, Sang-Min LEE, Gyu-Il CHA
  • Publication number: 20230196157
    Abstract: A quantum simulation apparatus according to an embodiment of the present disclosure includes a quantum circuit distributor configured to receive and transfer a plurality of quantum circuits, and a multi-quantum register controller configured to control independent allocation and execution of the input quantum circuits into multi-quantum registers supporting a reduced quantum state space, wherein the multi-quantum register provides the reduced quantum state space with respect to a real quantum state having a physical reality with an amplitude value that is not 0 in a wide-area quantum state space.
    Type: Application
    Filed: July 20, 2022
    Publication date: June 22, 2023
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ki Sung JIN, Gyu Il CHA, Chang Dae KIM
  • Publication number: 20230129967
    Abstract: A quantum computing system according to an embodiment of the present disclosure includes a logical qubit quantum compiler configured to receive a specific quantum code and to output a quantum kernel based on a quantum basic operation command, a logical qubit quantum kernel executor configured to generate a plurality of physical qubit quantum commands based on the quantum kernel, and a physical qubit quantum system configured to receive the physical qubit quantum command and to perform a physical quantum operation.
    Type: Application
    Filed: August 31, 2022
    Publication date: April 27, 2023
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Soo Cheol OH, Chei Yol KIM, Jin Ho ON, Sang Min LEE, Gyu Il CHA
  • Patent number: 11175960
    Abstract: A method and apparatus are disclosed which relate generally to worker-scheduling technology in a serverless cloud-computing environment, and more particularly, to technology that allocates workers for executing functions on a micro-function platform which provides a function-level micro-service. The method and apparatus process a worker allocation task in a distributed manner as two-step pre-allocation schemes before a worker allocation request occurs, and pre-allocates workers required for a service using a function request period and a function execution time, thus minimizing scheduling costs incurred by worker allocation requests.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 16, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Ho Kim, Chei-Yol Kim, Jin-Ho On, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10983835
    Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 20, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chei-Yol Kim, Young-Ho Kim, Jin-Ho On, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10977007
    Abstract: An apparatus and method for executing a function. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors, and the at least one program is configured to determine whether it is possible to reengineer a user function source using interface description language (IDL) code, to generate a reengineered function source by reengineering the user function source, and to execute the reengineered function source.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 13, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho On, Young-Ho Kim, Chei-Yol Kim, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10783015
    Abstract: Disclosed herein are an apparatus and method for providing long-term function execution in a serverless environment. The method for providing long-term function execution in a serverless environment is performed by an apparatus for providing long-term function execution in a serverless environment, and includes registering a long-term function execution proxy when a long-term execution request is received from a client, allocating a long-term function executor corresponding to the long-term execution request, executing, by the long-term function execution proxy, a long-term function using the allocated long-term function executor, and storing execution results of the long-term function.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: September 22, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho On, Ki-Young Kim, Gyu-Il Cha
  • Publication number: 20200183744
    Abstract: A worker-scheduling method in a cloud-computing system and an apparatus for the same. The worker-scheduling method includes performing a first load-distribution operation of pre-creating template workers so as to process worker execution preparation loads in a distributed manner before a worker allocation request for function execution occurs, predicting a number of workers to be pre-allocated in consideration of variation in a worker allocation request period for each function, and performing a second load distribution operation of pre-allocating ready workers by performing worker upscaling on as many template workers as the number of workers to be pre-allocated.
    Type: Application
    Filed: September 26, 2019
    Publication date: June 11, 2020
    Inventors: Young-Ho KIM, Chei-Yol KIM, Jin-Ho ON, Su-Min JANG, Gyu-Il CHA
  • Publication number: 20200183746
    Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.
    Type: Application
    Filed: October 21, 2019
    Publication date: June 11, 2020
    Inventors: Chei-Yol KIM, Young-Ho KIM, Jin-Ho ON, Su-Min JANG, Gyu-Il CHA
  • Publication number: 20200183657
    Abstract: An apparatus and method for executing a function. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors, and the at least one program is configured to determine whether it is possible to reengineer a user function source using interface description language (IDL) code, to generate a reengineered function source by reengineering the user function source, and to execute the reengineered function source.
    Type: Application
    Filed: September 19, 2019
    Publication date: June 11, 2020
    Inventors: Jin-Ho ON, Young-Ho KIM, Chei-Yol KIM, Su-Min JANG, Gyu-Il CHA
  • Publication number: 20190179684
    Abstract: Disclosed herein are an apparatus and method for providing long-term function execution in a serverless environment. The method for providing long-term function execution in a serverless environment is performed by an apparatus for providing long-term function execution in a serverless environment, and includes registering a long-term function execution proxy when a long-term execution request is received from a client, allocating a long-term function executor corresponding to the long-term execution request, executing, by the long-term function execution proxy, a long-term function using the allocated long-term function executor, and storing execution results of the long-term function.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Jin-Ho ON, Ki-Young KIM, Gyu-Il CHA
  • Patent number: 9509562
    Abstract: There are provided a method of providing a dynamic node service and a device using the same. The method of providing a dynamic node service that is operated in a fabric controller includes receiving a dynamic node service request, selecting a plurality of system resources including at least one processing unit from among system resources connected with a fabric switch corresponding to the dynamic node service request, and configuring a dynamic node by connecting the plurality of selected system resources to each other through control of the fabric switch. Therefore, it is possible to provide the dynamic node having performance satisfying a user's request.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 29, 2016
    Assignee: ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Gyu Il Cha
  • Publication number: 20160085450
    Abstract: The present invention relates to technology for providing a remote memory, and more particularly, to a system for providing a remote memory which may enable an application in a high performance computing system to use a physical memory of a remote computing node like a local memory of a computing node in which the corresponding application is executed, and a temporary page pool operating method for providing a remote memory.
    Type: Application
    Filed: March 30, 2015
    Publication date: March 24, 2016
    Inventors: Shin Young AHN, Young Ho KIM, Eun Ji LIM, Gyu Il CHA
  • Patent number: 8949847
    Abstract: Disclosed herein are a resource manager node and a resource management method. The resource manager node includes a resource management unit, a resource policy management unit, a shared resource capability management unit, a shared resource status monitoring unit, and a shared resource allocation unit. The resource management unit performs an operation necessary for resource allocation when a resource allocation request is received. The resource policy management unit determines a resource allocation policy based on the characteristic of the task, and generates resource allocation information. The shared resource capability management unit manages the topology of nodes, information about the capabilities of resources, and resource association information. The shared resource status monitoring unit monitors and manages information about the status of each node and the use of allocated resources. The shared resource allocation unit sends a resource allocation request to at least one of the plurality of nodes.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young-Ho Kim, Gyu-Il Cha, Shin-Young Ahn, Eun-Ji Lim, Jin-Mee Kim, Seung-Jo Bae
  • Publication number: 20140355478
    Abstract: There are provided a method of providing a dynamic node service and a device using the same. The method of providing a dynamic node service that is operated in a fabric controller includes receiving a dynamic node service request, selecting a plurality of system resources including at least one processing unit from among system resources connected with a fabric switch corresponding to the dynamic node service request, and configuring a dynamic node by connecting the plurality of selected system resources to each other through control of the fabric switch. Therefore, it is possible to provide the dynamic node having performance satisfying a user's request.
    Type: Application
    Filed: October 25, 2013
    Publication date: December 4, 2014
    Applicant: ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Gyu Il CHA
  • Patent number: 8850158
    Abstract: Disclosed is an apparatus for processing a remote page fault included in an optional local node within a cluster system configuring a large integration memory (CVM) by integrating individual memories of a plurality of nodes. The apparatus includes a memory including a CVM-map, a node memory information table, a virtual memory area, and a CVM page table, and a main controller mapping the large integration memory to an address space of a process when a user process requests memory allocation.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun Ji Lim, Gyu Il Cha, Young Ho Kim, Dong Jae Kang, Sung In Jung