Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

Abstract: In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

Abstract: The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

Abstract: The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.