Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: A substrate can include a feature pattern included in an integrated circuit on the substrate and an in-situ metrology pattern spaced apart from the feature pattern on the substrate, the in-situ metrology pattern and the feature pattern both configured to have equal heights relative to a surface of the substrate.

Abstract: A substrate can include a feature pattern included in an integrated circuit on the substrate and an in-situ metrology pattern spaced apart from the feature pattern on the substrate, the in-situ metrology pattern and the feature pattern both configured to have equal heights relative to a surface of the substrate.