Abstract: A Database method for a B+ tree based on a PRAM. The database method divides each node into two areas, area 1 and area 2. A key value is inserted/retrieved/deleted for the each node. Inserting the key value requires firstly inserting a new key value to area 2 if area 2 in the node is not in a full state. Retrieving the key value requires identifying whether the node is a leaf node. If the node is a leaf node, the key value is retrieved from area 1 and area 2 sequentially. Deleting the key value requires merging area 1 and area 2 in the node, and deleting the key value in the merged node. The method enhances durability and data processing capability.

Abstract: The following description relates to a virtual memory system, and a virtual memory system based on a storage device supporting massive storage input/output with improved system feature by corresponding a page size, i.e., an elementary unit of a virtual memory with a read/write unit of a storage device that supports massive storage input/output (I/O).

Abstract: The following description provides method for controlled collision of hash algorithm based on NAND flash memory improving data process performance by applying a hash structure on an optimized data structure in a NAND flash memory, using a coalesced chaining scheme. Further, the following description provides a method for controlled collision of hash algorithm based on NAND flash memory including a) setting one bucket size and an NAND flash memory page size identical; and b) storing a record regarding a plurality of hash values in the one bucket in NAND flash memory based hash index method. Further, when using a coalesced chaining and bucket separation scheme on a coalesced chaining scheme, storage space smaller than the separation chaining scheme, fast insert, fast retrieving are all possible, thereby data processing may be improved.

Abstract: A memory device includes a data block storing first data, and a log block storing second data that is an updated value of the first data. A spare area of the log block stores a first mapping table including mapping information between the first data and the second data.

Abstract: There is provided a Database method for a B+ tree based on a PRAM. The database method is characterized of dividing each node into area 1 and area 2; inserting/retrieving/deleting a certain key value for the each node. Inserting a key value is characterized of firstly inserting a new key value to area 2, if area 2 in the node is not in a full state. Retrieving a key value is characterized of identifying whether the node is a leaf node; and if the node is a leaf node, retrieving area 1 and area 2 sequentially. Deleting a key value is characterized of: merging area 1 and area 2 in the node; and deleting a key value in the merged node. Therefore, the present disclosure provides advantages of enhancing durability and data processing capability.

Abstract: Provided are a load balancing method and a load balancing apparatus in a symmetric multi-processor system. The load balancing method includes selecting at least two processors based on a load between a plurality of processors, from among the plurality of processors, migrating a predetermined task stored in a run queue of a first processor to a migration queue of a second processor, and migrating the predetermined task stored in the migration queue of the second processor to a run queue of the second processor. Accordingly, a run queue of a processor is not blocked while migrating a task, an immediate response of the run queue is possible, and a waiting time of a scheduler is reduced. Consequently, the scheduler can speedily perform context switching, and thus performance of the entire operating system is improved.

Abstract: The present disclosure relates to an electronic device for storing data on PRAM and a memory control method thereof The electronic device of the present disclosure comprises: a nonvolatile memory in which data is stored; a volatile memory in which an address conversion table of a nonvolatile memory is stored; and a controller that stores data on a nonvolatile memory by referencing an address conversion table of a nonvolatile memory stored on a volatile memory. Due to this, a nonvolatile memory having limitative number of write and read such as PRAM can be operated more effectively.

Abstract: Provided are an apparatus for reconfiguring a mapping method and a scheduling method in a reconfigurable multi-processor system. A single function is mapped to a reconfigurable processor. When a task is created in the reconfigurable multi-processor system, a function of the task is dynamically mapped to a host processor or a reconfigurable processor, thereby removing temporal sharing between functions on the reconfigurable processor and thus reducing the number of times reconfiguration is performed. The overhead of the reconfigurable processor is minimized and the reconfigurable processor is optimized for a dynamic multi-application environment.

Abstract: A multi-tasking method performs a plurality of tasks according to priority of each of the plurality of tasks. It is determined whether a resource that is to be used by a current task is being used by another task, a priority of the current task is compared to a priority of the task that is using the resource according to a result of the determination, and according to a result of the comparison, the priority of the task that is using the resource is increased to a highest priority of priorities of all tasks trying to occupy a CPU. Accordingly, conventional problems in the BPI and IIP schemes can be solved.

Abstract: Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking.

Abstract: A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory.

Abstract: A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.

Abstract: A storage management system and a storage management method are provided. The storage management system includes a host, a memory buffer, a plurality of storage blocks, and an input/output bus to perform an interface function among the host, the memory buffer, and the plurality of storage blocks, wherein each of the plurality of storage blocks is connected with the input/output bus via a corresponding channel, and the plurality of storage blocks is managed for each channel group generated by grouping at least one channel.

Abstract: A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.

Abstract: A memory device and a method for managing the memory device is provided. The memory device includes a flash memory including a plurality of pages, a non-volatile RAM storing a first mapping table between a physical page address and a logical page address for each page of the plurality of pages, and a volatile RAM storing a second mapping table between the physical page address and the logical page address for each page of the plurality of pages.

Abstract: A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM.

Abstract: A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory.

Abstract: A storage management system and a storage management method are provided. The storage management system includes a host, a memory buffer, a plurality of storage blocks, and an input/output bus to perform an interface function among the host, the memory buffer, and the plurality of storage blocks, wherein each of the plurality of storage blocks is connected with the input/output bus via a corresponding channel, and the plurality of storage blocks is managed for each channel group generated by grouping at least one channel.

Abstract: Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking.

Abstract: Provided are a load balancing method and a load balancing apparatus in a symmetric multi-processor system. The load balancing method includes selecting at least two processors based on a load between a plurality of processors, from among the plurality of processors, migrating a predetermined task stored in a run queue of a first processor to a migration queue of a second processor, and migrating the predetermined task stored in the migration queue of the second processor to a run queue of the second processor. Accordingly, a run queue of a processor is not blocked while migrating a task, an immediate response of the run queue is possible, and a waiting time of a scheduler is reduced. Consequently, the scheduler can speedily perform context switching, and thus performance of the entire operating system is improved.