Patents by Inventor Gyu-Sun Moon

Gyu-Sun Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6822703
    Abstract: A polycrystalline silicon TFT for an LCD and a manufacturing method thereof is disclosed. The TFT comprises an active pattern formed on a substrate, a gate insulating layer formed on the substrate including the active pattern, a gate line formed on the gate insulating layer to be crossed with the active pattern and including a gate electrode for defining the first impurity region, a second impurity region and a channel region, an insulating interlayer formed on the gate insulating layer including the gate line, a data line formed on the insulating interlayer and connected to the second impurity region through the first contact hole which is formed through the gate insulating layer and the insulating interlayer on the second impurity region and a pixel electrode formed on the same insulating interlayer as the data line and connected with the first impurity region through a second contact hole which is formed through the gate insulating layer and the insulating interlayer on the first impurity region.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: November 23, 2004
    Assignee: Samsung Electronics Co., LTD
    Inventors: Chang-Won Hwang, Woo-Suk Chung, Tae-Hyeong Park, Hyun-Jae Kim, Gyu-Sun Moon, Sook-Young Kang
  • Publication number: 20020158995
    Abstract: A polycrystalline silicon TFT for an LCD and a manufacturing method thereof is disclosed. The TFT comprises an active pattern formed on a substrate, a gate insulating layer formed on the substrate including the active pattern, a gate line formed on the gate insulating layer to be crossed with the active pattern and including a gate electrode for defining the first impurity region, a second impurity region and a channel region, an insulating interlayer formed on the gate insulating layer including the gate line, a data line formed on the insulating interlayer and connected to the second impurity region through the first contact hole which is formed through the gate insulating layer and the insulating interlayer on the second impurity region and a pixel electrode formed on the same insulating interlayer as the data line and connected with the first impurity region through a second contact hole which is formed through the gate insulating layer and the insulating interlayer on the first impurity region.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 31, 2002
    Inventors: Chang-Won Hwang, Woo-Suk Chung, Tae-Hyeong Park, Hyun-Jae Kim, Gyu-Sun Moon, Sook-Young Kang