Abstract: A phase locked loop circuit comprising a first counter for dividing a reference frequency at a division ratio predetermined or determined by an input unit, a second counter for dividing a frequency of an output signal from the phase locked loop circuit at a division ratio predetermined or determined by a different input unit, a phase detector for inputting output signals from the first and second counters and generating a voltage based on a phase difference between the inputted signals, a low pass filter for low pass filtering an output signal from the phase detector, and a voltage controlled oscillator for generating a frequency signal proportioned to an output voltage from the low pass filter. The phase locked loop circuit further comprises an unlock detector for generating a control signal for synchronization of one of the first and second counters with an earlier phase in response to an unlocked signal from the phase detector.