Patents by Inventor Gyu-tae Park

Gyu-tae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294379
    Abstract: A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: May 6, 2025
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Jae An
  • Patent number: 12119822
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Grant
    Filed: August 16, 2023
    Date of Patent: October 15, 2024
    Assignee: SK hynix Inc.
    Inventors: Young Ouk Kim, Gyu Tae Park
  • Patent number: 12074602
    Abstract: A duty correction circuit comprises a first delay circuit, a second delay circuit, a bang-bang driver, a duty detection circuit, and a delay control circuit. The first delay circuit delays an input clock signal to generate a first delayed clock signal. The second delay circuit delays the input clock signal based on a delay control signal to generate a second delayed clock signal. The bang-bang driver generates first and second driving clock signals from the first and second delayed clock signals based on a locking signal and a duty detection signal. The duty detection circuit may detect duty cycles of the first and second driving clock signals and generate the duty detection signal. The delay control circuit may generate the delay control signal and the locking signal based on the duty detection signal.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: August 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Suk Seo
  • Publication number: 20240194201
    Abstract: An approach for controlling method of an electronic device is provided. The approach acquires voice information and image information for setting an action to be executed according to a condition, the voice information and the image information being respectively generated from a voice and a behavior associated with the voice of a user. The approach determines an event to be detected according to the condition and a function to be executed according to the action when the event is detected, based on the acquired voice information and the acquired image information. The approach determines at least one detection resource to detect the determined event. In response to the at least one determined detection resource detecting at least one event satisfying the condition, the approach executes the function according to the action.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-chul SOHN, Gyu-tae Park, Ki-Beom Lee, Jong-ryul Lee
  • Publication number: 20240072810
    Abstract: A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.
    Type: Application
    Filed: December 20, 2022
    Publication date: February 29, 2024
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Young Jae AN
  • Patent number: 11907009
    Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: Gyu Tae Park
  • Patent number: 11908465
    Abstract: An approach for controlling method of an electronic device is provided. The approach acquires voice information and image information for setting an action to be executed according to a condition, the voice information and the image information being respectively generated from a voice and a behavior associated with the voice of a user. The approach determines an event to be detected according to the condition and a function to be executed according to the action when the event is detected, based on the acquired voice information and the acquired image information. The approach determines at least one detection resource to detect the determined event. In response to the at least one determined detection resource detecting at least one event satisfying the condition, the approach executes the function according to the action.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-chul Sohn, Gyu-tae Park, Ki-beom Lee, Jong-ryul Lee
  • Patent number: 11875574
    Abstract: Disclosed is an object recognition method including: obtaining a first RGB image by using a camera; predicting at least one first region, in which an object is unrecognizable, in the first RGB image based on brightness information of the first RGB image; determining at least one second region, in which an object exists, from among the at least one first region, based on object information obtained through a dynamic vision sensor; obtaining an enhanced second RGB image by controlling photographic configuration information of the camera in relation to the at least one second region; and recognizing the object in the second RGB image.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu-tae Park, Sejin Kwak
  • Patent number: 11862154
    Abstract: An approach for controlling method of an electronic device is provided. The approach acquires voice information and image information for setting an action to be executed according to a condition, the voice information and the image information being respectively generated from a voice and a behavior associated with the voice of a user. The approach determines an event to be detected according to the condition and a function to be executed according to the action when the event is detected, based on the acquired voice information and the acquired image information. The approach determines at least one detection resource to detect the determined event. In response to the at least one determined detection resource detecting at least one event satisfying the condition, the approach executes the function according to the action.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-chul Sohn, Gyu-tae Park, Ki-beom Lee, Jong-ryul Lee
  • Publication number: 20230396239
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 7, 2023
    Applicant: SK hynix Inc.
    Inventors: Young Ouk KIM, Gyu Tae PARK
  • Publication number: 20230336164
    Abstract: A duty correction circuit comprises a first delay circuit, a second delay circuit, a bang-bang driver, a duty detection circuit, and a delay control circuit. The first delay circuit delays an input clock signal to generate a first delayed clock signal. The second delay circuit delays the input clock signal based on a delay control signal to generate a second delayed clock signal. The bang-bang driver generates first and second driving clock signals from the first and second delayed clock signals based on a locking signal and a duty detection signal. The duty detection circuit may detect duty cycles of the first and second driving clock signals and generate the duty detection signal. The delay control circuit may generate the delay control signal and the locking signal based on the duty detection signal.
    Type: Application
    Filed: November 8, 2022
    Publication date: October 19, 2023
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Young Suk SEO
  • Patent number: 11777474
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Young Ouk Kim, Gyu Tae Park
  • Patent number: 11704827
    Abstract: An electronic apparatus and method for assisting with driving of a vehicle are provided. The electronic apparatus includes: a processor configured to execute one or more instructions stored in a memory, to: obtain a surrounding image of the vehicle via at least one sensor, recognize an object from the obtained surrounding image, obtain three-dimensional (3D) coordinate information for the object by using the at least one sensor, determine a number of planar regions constituting the object, based on the 3D coordinate information corresponding to the object, determine whether the object is a real object, based on the number of planar regions constituting the object, and control a driving operation of the vehicle based on a result of the determining whether the object is the real object.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kibeom Lee, Gyu-tae Park, Boseok Moon
  • Publication number: 20230041331
    Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 9, 2023
    Applicant: SK hynix Inc.
    Inventor: Gyu Tae PARK
  • Patent number: 11513553
    Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Gyu Tae Park
  • Patent number: 11496136
    Abstract: A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Patent number: 11483004
    Abstract: A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second clock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Publication number: 20220247390
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Applicant: SK hynix Inc.
    Inventors: Young Ouk KIM, Gyu Tae PARK
  • Patent number: 11349457
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 31, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Ouk Kim, Gyu Tae Park
  • Publication number: 20220123755
    Abstract: A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second dock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.
    Type: Application
    Filed: November 17, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Young Ouk KIM