Patents by Inventor Gyu-tae Park

Gyu-tae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11513553
    Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Gyu Tae Park
  • Patent number: 11495505
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 8, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Patent number: 11496136
    Abstract: A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Patent number: 11483004
    Abstract: A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second clock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Patent number: 11482496
    Abstract: In one example, an electronic device, comprises a first substrate comprising a first conductive structure, a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate, a first electronic component between the first substrate and the second substrate, a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering the vertical interconnect. A vertical port on the first electronic component is exposed by an aperture of the first substrate. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 25, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Myung Jea Choi, Gyu Wan Han, Gi Tae Lim, Dong Joo Park, Ji Hun Yi, Jin Young Khim
  • Patent number: 11430723
    Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 30, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
  • Publication number: 20220247390
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Applicant: SK hynix Inc.
    Inventors: Young Ouk KIM, Gyu Tae PARK
  • Patent number: 11398455
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 26, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee
  • Publication number: 20220213247
    Abstract: Disclosed is a method for producing a diene-based graft copolymer resin, and a diene-based graft copolymer resin produced therefrom, the method including: adding, into a reactor, a polymerization solution containing a diene-based rubber polymer, an aromatic vinyl-based monomer, a vinyl cyan-based monomer, a polymerization initiator, and a reaction solvent, and polymerizing the polymerization solution to prepare a polymer; recovering a solution containing unreacted monomers and a reaction solvent from the polymerization solution, dispersing a releasing agent in the recovered solution, and then adding the solution into the front end of a volatilization tank; and removing the unreacted monomers and the reaction solvent from the volatilization tank.
    Type: Application
    Filed: October 7, 2020
    Publication date: July 7, 2022
    Applicant: LG CHEM, LTD.
    Inventors: Ji Uk JANG, Dae Woo LEE, Jae Bum SEO, Jung Tae PARK, Gyu Sun KIM
  • Patent number: 11349457
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 31, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Ouk Kim, Gyu Tae Park
  • Publication number: 20220123755
    Abstract: A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second dock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.
    Type: Application
    Filed: November 17, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Young Ouk KIM
  • Publication number: 20220094339
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Application
    Filed: February 8, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventors: Young Ouk KIM, Gyu Tae PARK
  • Patent number: 11256285
    Abstract: A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Gyu Tae Park
  • Patent number: 11227594
    Abstract: A method, performed by a device, of providing a response to a user's voice input, includes capturing, via a camera of the device, an image including at least one object; activating a microphone of the device as the image is captured; receiving, via the microphone, the user's voice input for the object; determining the intention of the user with respect to the object by analyzing the received voice input; and providing a response regarding the at least one object based on the determined intention of the user.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-ryul Lee, Young-chul Sohn, Gyu-tae Park, Ki-beom Lee
  • Publication number: 20210350145
    Abstract: Disclosed is an object recognition method including: obtaining a first RGB image by using a camera; predicting at least one first region, in which an object is unrecognizable, in the first RGB image based on brightness information of the first RGB image; determining at least one second region, in which an object exists, from among the at least one first region, based on object information obtained through a dynamic vision sensor; obtaining an enhanced second RGB image by controlling photographic configuration information of the camera in relation to the at least one second region; and recognizing the object in the second RGB image.
    Type: Application
    Filed: September 26, 2019
    Publication date: November 11, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu-tae PARK, Sejin KWAK
  • Patent number: 11146275
    Abstract: A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Jin Il Chung
  • Publication number: 20210271288
    Abstract: A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 2, 2021
    Applicant: SK hynix Inc.
    Inventors: Young Suk SEO, Gyu Tae PARK
  • Patent number: 11050413
    Abstract: A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Publication number: 20210091772
    Abstract: A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.
    Type: Application
    Filed: April 27, 2020
    Publication date: March 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Jin Il CHUNG
  • Publication number: 20200401180
    Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.
    Type: Application
    Filed: December 6, 2019
    Publication date: December 24, 2020
    Applicant: SK hynix Inc.
    Inventor: Gyu Tae PARK