Patents by Inventor Gyu Wan Han
Gyu Wan Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230110213Abstract: In one example, an electronic device, comprises a first substrate comprising a first conductive structure, a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate, a first electronic component between the first substrate and the second substrate, a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering the vertical interconnect. A vertical port on the first electronic component is exposed by an aperture of the first substrate. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: October 25, 2022Publication date: April 13, 2023Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Myung Jea Choi, Gyu Wan Han, Gi Tae Lim, Dong Joo Park, Ji Hun Yi, Jin Young Khim
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Publication number: 20230070922Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: November 8, 2022Publication date: March 9, 2023Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Publication number: 20220415769Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
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Patent number: 11495505Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: September 11, 2020Date of Patent: November 8, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Patent number: 11482496Abstract: In one example, an electronic device, comprises a first substrate comprising a first conductive structure, a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate, a first electronic component between the first substrate and the second substrate, a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering the vertical interconnect. A vertical port on the first electronic component is exposed by an aperture of the first substrate. Other examples and related methods are also disclosed herein.Type: GrantFiled: October 16, 2020Date of Patent: October 25, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Myung Jea Choi, Gyu Wan Han, Gi Tae Lim, Dong Joo Park, Ji Hun Yi, Jin Young Khim
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Patent number: 11430723Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.Type: GrantFiled: October 1, 2018Date of Patent: August 30, 2022Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
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Patent number: 11398455Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: June 3, 2019Date of Patent: July 26, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee
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Publication number: 20220122921Abstract: In one example, an electronic device, comprises a first substrate comprising a first conductive structure, a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate, a first electronic component between the first substrate and the second substrate, a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering the vertical interconnect. A vertical port on the first electronic component is exposed by an aperture of the first substrate. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: October 16, 2020Publication date: April 21, 2022Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Myung Jea Choi, Gyu Wan Han, Gi Tae Lim, Dong Joo Park, Ji Hun Yi, Jin Young Khim
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Publication number: 20210288010Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.Type: ApplicationFiled: March 5, 2021Publication date: September 16, 2021Inventors: Gyu Wan Han, Jin Seong Kim, Byong Woo Cho
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Patent number: 11049828Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.Type: GrantFiled: March 23, 2016Date of Patent: June 29, 2021Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Gyu Wan Han, Jin Seong Kim, Byong Woo Cho
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Publication number: 20200411397Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Publication number: 20200381395Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee
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Publication number: 20190043793Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.Type: ApplicationFiled: October 1, 2018Publication date: February 7, 2019Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
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Patent number: 10090230Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.Type: GrantFiled: September 25, 2014Date of Patent: October 2, 2018Assignee: Amkor Technology, Inc.Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
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Publication number: 20160284657Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.Type: ApplicationFiled: March 23, 2016Publication date: September 29, 2016Inventors: Gyu Wan Han, Jin Seong Kim, Byong Woo Cho
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Publication number: 20150084185Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
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Publication number: 20130234973Abstract: The present invention relates to a touch screen panel and to an image display device including same. The touch screen panel comprises: a first sensing wire pattern layer in which a plurality of first sensing wire pattern lines are formed in a first diagonal direction; a second sensing wire pattern layer in which a plurality of second sensing wire pattern lines are formed in a second diagonal direction so as to form a preset angle with the first sensing wires; and an insulation layer for providing insulation between the 1st sensing wire pattern layer and the 2nd sensing wire pattern layer. Since capacitive touch sensing wire pattern lines are disposed diagonally with a certain angle therebetween, the number of wires arranged on the major axis of the bezel of the touch screen panel can be reduced when compared to the resolution of touch screen panels of prior art in which the arrangement is perpendicular.Type: ApplicationFiled: November 22, 2011Publication date: September 12, 2013Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: Tae Whan Kim, Gyu Wan Han, Su Hyeong Park