Abstract: A probe card, for testing an electrical characteristic of a device under test (DUT) including a plurality of semiconductor devices, includes a substrate, a first probe pin disposed on a surface of the substrate and including a tip portion capable of contacting a pad of the DUT, and a second probe pin disposed on the surface of the substrate and including a tip portion capable of contacting the pad of the DUT. The first probe pin protrudes further than the second probe pin protrudes from the surface of the substrate in a first direction that is substantially perpendicular to the surface of the substrate.

Abstract: A probe card assembly is provided as follows. A tile fixing substrate is disposed on a printed circuit board. A plurality of ceramic tiles is detachably attached to the tile fixing substrate. Each of the plurality of ceramic tiles comprises a plurality of probes. A plurality of alignment marks is fixed to the tile fixing substrate.

Abstract: A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.

Abstract: A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.

Abstract: A probe includes a beam and at least two tips. The beam transmits test signals to a device under test (DUT). The at least two tips are arranged on a first end portion of the beam in a direction at a predetermined angle to a length direction of the beam and contacts adjacent terminals of the DUT. The beam has a larger width that exceeds a sum of widths of the at least two tips in a width direction of the beam such that the probe has an improved current carrying capacity and is prevented from being damaged due to overcurrent.

Abstract: A probe includes a beam and at least two tips. The beam transmits test signals to a device under test (DUT). The at least two tips are arranged on a first end portion of the beam in a direction at a predetermined angle to a length direction of the beam and contacts adjacent terminals of the DUT. The beam has a larger width that exceeds a sum of widths of the at least two tips in a width direction of the beam such that the probe has an improved current carrying capacity and is prevented from being damaged due to overcurrent.

Abstract: A probe card assembly is provided as follows. A tile fixing substrate is disposed on a printed circuit board. A plurality of ceramic tiles is detachably attached to the tile fixing substrate. Each of the plurality of ceramic tiles comprises a plurality of probes. A plurality of alignment marks is fixed to the tile fixing substrate.

Abstract: A probe card, for testing an electrical characteristic of a device under test (DUT) including a plurality of semiconductor devices, includes a substrate, a first probe pin disposed on a surface of the substrate and including a tip portion capable of contacting a pad of the DUT, and a second probe pin disposed on the surface of the substrate and including a tip portion capable of contacting the pad of the DUT. The first probe pin protrudes further than the second probe pin protrudes from the surface of the substrate in a first direction that is substantially perpendicular to the surface of the substrate.

Abstract: An electrical signal transmission module includes a plurality of optical signal lines and a plurality of electrical signal lines. The plurality of optical signal lines converting a first externally input electrical signal into an optical signal, transmitting the optical signal, converting the optical signal back into the first electrical signal, and outputting the first electrical signal. The plurality of electrical signal lines transmitting a second externally input electrical signal and outputting the second electrical signal.

Abstract: An electrical signal transmission module includes a plurality of optical signal lines and a plurality of electrical signal lines. The plurality of optical signal lines converting a first externally input electrical signal into an optical signal, transmitting the optical signal, converting the optical signal back into the first electrical signal, and outputting the first electrical signal. The plurality of electrical signal lines transmitting a second externally input electrical signal and outputting the second electrical signal.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.