Patents by Inventor Gyu-Hwan AHN

Gyu-Hwan AHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014209
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Patent number: 11804483
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 31, 2023
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Patent number: 11600518
    Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Soo Kim, Chae Ho Na, Gyu Hwan Ahn, Dong Hyun Roh, Sang Jin Hyun
  • Publication number: 20220262673
    Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Chae Ho NA, Sung Soo KIM, Gyu Hwan AHN, Dong Hyun ROH
  • Patent number: 11328949
    Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae Ho Na, Sung Soo Kim, Gyu Hwan Ahn, Dong Hyun Roh
  • Publication number: 20210257250
    Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Sung Soo KIM, Chae Ho NA, Gyu Hwan AHN, Dong Hyun ROH, Sang Jin HYUN
  • Publication number: 20210193656
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 24, 2021
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Patent number: 11018050
    Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Soo Kim, Chae Ho Na, Gyu Hwan Ahn, Dong Hyun Roh, Sang Jin Hyun
  • Patent number: 10950602
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 16, 2021
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Publication number: 20200321241
    Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 8, 2020
    Inventors: CHAE HO NA, SUNG SOO KIM, GYU HWAN AHN, DONG HYUN ROH
  • Patent number: 10790282
    Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Jung Choi, Dong-Hyun Roh, Sung-Soo Kim, Gyu-Hwan Ahn, Sang-Jin Hyun
  • Publication number: 20200098751
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Application
    Filed: May 2, 2019
    Publication date: March 26, 2020
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Publication number: 20200075399
    Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.
    Type: Application
    Filed: April 17, 2019
    Publication date: March 5, 2020
    Inventors: Sung Soo KIM, Chae Ho NA, Gyu Hwan AHN, Dong Hyun ROH, Sang Jin HYUN
  • Publication number: 20200020691
    Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.
    Type: Application
    Filed: December 21, 2018
    Publication date: January 16, 2020
    Inventors: Soo-Jung CHOI, Dong-Hyun ROH, Sung-Soo KIM, Gyu-Hwan AHN, Sang-Jin HYUN