Patents by Inventor Gyu-Hwan Oh
Gyu-Hwan Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10833124Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.Type: GrantFiled: April 16, 2018Date of Patent: November 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyo Seop Kim, Chang Woo Sun, Gyu Hwan Oh, Joon Kim, Joon Youn Hwang
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Patent number: 10692933Abstract: A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.Type: GrantFiled: March 20, 2019Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Yong-Jin Park, Jun-Hwan Paik, Gyu-Hwan Oh
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Publication number: 20200066799Abstract: A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.Type: ApplicationFiled: March 20, 2019Publication date: February 27, 2020Inventors: Dong-Jun Seong, Yong-Jin Park, Jun-Hwan Paik, Gyu-Hwan Oh
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Publication number: 20190109175Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.Type: ApplicationFiled: April 16, 2018Publication date: April 11, 2019Inventors: Kyo Seop Kim, Chang Woo Sun, Gyu Hwan Oh, Joon Kim, Joon Youn Hwang
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Patent number: 9196827Abstract: A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.Type: GrantFiled: July 12, 2012Date of Patent: November 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Doo-Hwan Park, Young-Kuk Kim
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Patent number: 9130160Abstract: A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode.Type: GrantFiled: July 21, 2014Date of Patent: September 8, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Gyu-Hwan Oh
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Patent number: 8884263Abstract: A diode may be formed within a molding layer on a substrate. A conductive buffer pattern having a greater planar area than the diode may be on the diode and molding layer. An electrode structure may be on the conductive buffer pattern. A data storage pattern may be on the electrode structure. One lateral surface of the conductive buffer pattern may be vertically aligned with one lateral surface of the electrode structure.Type: GrantFiled: June 14, 2012Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Doo-Hwan Park
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Publication number: 20140326942Abstract: A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode.Type: ApplicationFiled: July 21, 2014Publication date: November 6, 2014Inventor: Gyu-Hwan OH
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Patent number: 8872148Abstract: A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.Type: GrantFiled: January 7, 2013Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Hwan Park, Gyu-Hwan Oh, Jeong-Min Park, Kyung-Min Chung
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Patent number: 8841643Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.Type: GrantFiled: September 23, 2011Date of Patent: September 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Shin-Jae Kang, Sug-Woo Jung, Dong-Hyun Im, Chan-Mi Lee
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Patent number: 8830739Abstract: A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode.Type: GrantFiled: March 9, 2013Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Gyu-Hwan Oh
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Patent number: 8790976Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.Type: GrantFiled: July 15, 2013Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
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Patent number: 8785213Abstract: A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.Type: GrantFiled: June 12, 2012Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Doo-Hwan Park
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Patent number: 8703573Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other, forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.Type: GrantFiled: March 16, 2012Date of Patent: April 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Dong-Hyun Kim, Kyung-Min Chung, Dong-Hyun Im
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Patent number: 8680500Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.Type: GrantFiled: June 13, 2012Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Byoung-Jae Bae, Dong-Hyun Im, Doo-Hwan Park
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Publication number: 20130336046Abstract: A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode.Type: ApplicationFiled: March 9, 2013Publication date: December 19, 2013Inventor: Gyu-Hwan Oh
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Publication number: 20130302966Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
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Patent number: 8557627Abstract: A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material.Type: GrantFiled: January 28, 2013Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Ho Oh, Jeong-Hee Park, Man-Sug Kang, Byoung-Deog Choi, Gyu-Hwan Oh, Hye-Young Park, Doo-Hwan Park
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Patent number: 8551805Abstract: A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.Type: GrantFiled: May 11, 2012Date of Patent: October 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Doo-Hwan Park, Kyung-Min Chung
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Publication number: 20130256621Abstract: A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.Type: ApplicationFiled: January 7, 2013Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo-Hwan Park, Gyu-Hwan Oh, Jeong-Min Park, Kyung-Min Chung