Abstract: Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.

Abstract: Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.

Abstract: Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.

Abstract: A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

Abstract: A duty cycle correction (DCC) circuit receives first and second clock signals and outputs a duty cycle adjusted clock signal, and a control circuit detects a process variation and controls respective slew rates of the first and second clock signals based on the detected process variation. The DCC circuit may include a first inverter having an input that receives the first clock signal, a second inverter having an input that receives the second clock signal, a third inverter having an input commonly connected to outputs of the first and second inverters, a first variable capacitor connected between the input of the first inverter and a ground voltage, and a second variable capacitor connected between the input of the first inverter and the ground voltage. In this case, the respective capacitance values of the first and second variable capacitors are set by the control circuit.

Abstract: An embodiment of a differential output driver includes a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal. The differential output driver also includes a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal, and a second detected voltage difference between the reference voltage and the inverted output signal.

Abstract: Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Abstract: A delay locked loop capable of performing a reliable locking operation is provided that includes a phase controller, which controls a phase of a reference clock signal in response to first and second phase control signals, and a phase detector, which compares the phase of the reference clock signal to a phase of a feedback clock signal and outputs the first and second phase control signals to match the phase of the reference clock signal and the phase of the feedback clock signal, where the phase detector keeps the length of a detecting window constant in response to a current signal despite changes in external voltage, temperature, and the manufacturing process.

Abstract: A semiconductor memory device and a method thereof are provided. The example method may include determining whether a currently tested cell is defective and repairing the currently tested cell, if the currently tested cell is determined to be defective, before determining whether a next tested cell is defective. The example method may be performed by a semiconductor memory device including a built-in self-test (BIST) circuit and a repair control circuit. Alternatively, the example method may be performed by a semiconductor memory device including a BIST circuit, a repair control circuit and a storage device.

Abstract: A semiconductor device having a delay-locked loop includes: a variable delayer that delays a clock signal for a predetermined period of time to generate an internal clock signal; a normal pass that outputs data read from a memory cell outside the semiconductor device in response to the internal clock signal; a replica pass that has a substantial identical time delay to the normal pass and delays the internal clock signal to generate an output signal; and a phase detector that compares a phase of the clock signal with a phase of a predetermined feedback clock signal to control a time delay in the variable delayer. Here, the internal clock signal is output, instead of the output signal from the replica pass, as the predetermined feedback clock signal in a predetermined test mode.

Abstract: An embodiment of a differential output driver includes a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal. The differential output driver also includes a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal, and a second detected voltage difference between the reference voltage and the inverted output signal.

Abstract: In a delay locked loop (DLL) of a semiconductor memory device capable of compensating for delay of an internal clock signal by variation of driving strength of an output driver, a replica output driver exhibits the same delay amount as the delay amount as an output driver whose driving strength varies. A phase detector detects a phase difference between an internal clock signal which is delayed by the replica output driver, and an external clock signal. A control circuit generates a control signal in response to the output signal of the phase detector. A variable delay circuit, in response to the control signal, delays the external clock signal and generates the internal clock signal in synchronization with the external clock signal. Since the DLL has a replica output driver which can accurately track the delay of an internal clock signal by variation of the driving strength of an output driver in the feedback loop, output data can be accurately synchronized with an external clock signal.

Abstract: A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

Abstract: Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Abstract: A delay locked loop capable of performing a reliable locking operation is provided that includes a phase controller, which controls a phase of a reference clock signal in response to first and second phase control signals, and a phase detector, which compares the phase of the reference clock signal to a phase of a feedback clock signal and outputs the first and second phase control signals to match the phase of the reference clock signal and the phase of the feedback clock signal, where the phase detector keeps the length of a detecting window constant in response to a current signal despite changes in external voltage, temperature, and the manufacturing process.

Abstract: A semiconductor device having a delay-locked loop includes: a variable delayer that delays a clock signal for a predetermined period of time to generate an internal clock signal; a normal pass that outputs data read from a memory cell outside the semiconductor device in response to the internal clock signal; a replica pass that has a substantial identical time delay to the normal pass and delays the internal clock signal to generate an output signal; and a phase detector that compares a phase of the clock signal with a phase of a predetermined feedback clock signal to control a time delay in the variable delayer. Here, the internal clock signal is output, instead of the output signal from the replica pass, as the predetermined feedback clock signal in a predetermined test mode.

Abstract: In a delay locked loop (DLL) of a semiconductor memory device capable of compensating for delay of an internal clock signal by variation of driving strength of an output driver, a replica output driver exhibits the same delay amount as the delay amount as an output driver whose driving strength varies. A phase detector detects a phase difference between an internal clock signal which is delayed by the replica output driver, and an external clock signal. A control circuit generates a control signal in response to the output signal of the phase detector. A variable delay circuit, in response to the control signal, delays the external clock signal and generates the internal clock signal in synchronization with the external clock signal. Since the DLL has a replica output driver which can accurately track the delay of an internal clock signal by variation of the driving strength of an output driver in the feedback loop, output data can be accurately synchronized with an external clock signal.