Abstract: The present invention relates to a method and an apparatus for diagnosing low voltage of a secondary battery cell. The method for diagnosing low voltage of a secondary battery cell according to an embodiment of the present invention includes pre-aging a battery cell, charging the battery cell according to a preset charging condition, measuring a parameter for determining low voltage failure of the battery cell, comparing the measured parameter with a reference parameter, and performing formation when the battery cell is determined to be normal.

Abstract: A secondary battery comprises an electrode assembly, a can, and an insulator. The electrode assembly includes a first electrode, a separator, and a second electrode alternately stacked and wound. The can has an accommodation part accommodating the electrode assembly therein, and the can comprises a first can and a second can having cylindrical shapes open in a direction facing each other. The insulator insulates an overlapping portion between the first can and the second can. The first can is electrically connected to the first electrode, and the second can is electrically connected to the second electrode. The insulator has a short-circuit induction through-part defined by a through-hole or a cutoff line, such that a short circuit occurs between the first can and the second can through the short-circuit induction through-part when it is deformed in shape as heat or a pressure is applied to contract or expand the insulator.

Abstract: A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.

Abstract: A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.

Abstract: A semiconductor memory device includes an enable fuse unit configured to generate a repair enable signal corresponding to a cutting state of an enable fuse after a power-up operation starts, and an address fuse unit enabled in response to the repair enable signal, and configured to generate an output signal in response to an external address and whether or not an address fuse is programmed.

Abstract: According to the embodiment of the present invention, an infrared sensor chip may be provided that includes: a CMOS circuit board comprised of an active matrix, a row line selector and an output multiplexer; and a bolometer which is stacked on the CMOS circuit board and is comprised of an active cell and a reference cell, wherein, for the purpose of a parametric test for the bolometer at a wafer or chip state, the row line selector selects a cell to which a voltage is applied in the bolometer, and wherein the output multiplexer outputs current characteristics according to the voltage application.

Abstract: A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.

Abstract: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight to main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

Abstract: A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias.

Abstract: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight to main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

Abstract: A semiconductor memory device includes an enable fuse unit configured to generate a repair enable signal corresponding to a cutting state of an enable fuse after a power-up operation starts, and an address fuse unit enabled in response to the repair enable signal, and configured to generate an output signal in response to an external address and whether or not an address fuse is programmed.

Abstract: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

Abstract: A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.

Abstract: A fuse circuit of a semiconductor integrated apparatus includes first and second fuse blocks. The first fuse block includes a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged. The second plurality of fuses comprises fewer fuses than the first plurality of fuses. The second fuse block includes a second up fuse block where a third plurality of fuses are arranged, the third plurality of fuses comprising the same number of fuses as the second plurality of fuses, and a second down fuse block that includes a fourth plurality of fuses, the fourth plurality of fuses comprising the same number of fuses as the first plurality of fuses. The first up fuse block is opposite the second up fuse block and the first down fuse block is opposite the second down fuse block.

Abstract: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight lo main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

Abstract: A fuse circuit of a semiconductor integrated apparatus includes a first fuse block and a second fuse block. The first fuse block includes a first up fuse block that includes a plurality of fuses, and a first down fuse block that includes fuses less than the number of fuses of the first up fuse block. The second up fuse block includes a second up fuse block that includes the same number of fuses as the first down fuse block, and a second down fuse block that includes the same number of fuses as the first up fuse block. Structures of the first up fuse block and the first down fuse block are asymmetric, and the structures of the second up fuse block and the second down fuse block are asymmetric.

Abstract: Brassinosteriods are a kind of plant hormones, which are ubiquitously distributed throughout the plant kingdom and are functional in cell elongation and cell division at extremely low concentrations. However, the most important synthetic enzyme proteins and nucleic acids encoding the proteins regulating the final step of brassinosteroid biosynthesis have not been known. The inventors searched homological nucleotide sequences to ROT3, which the inventors had previously discovered, and found a nucleotide sequence that exhibits 51% identity to ROT3 gene. Examining the sequence, the inventors discovered that the sequence is a novel gene (CYP90D1, SEQ ID NO: 1), which encodes a factor regulating the final step of brassinosteroid biosynthesis, physiologically functional in regulating the size of plant. Furthermore, the inventors discovered that the CYP90D1 gene regulates the final step of the brassinosteroid biosynthesis in combination with ROT3 (=CYP90C1) gene, then accomplished the present invention.