Abstract: A semiconductor device includes: a power-gated logic circuit suitable for operating in response to a first power gating enable signal which is deactivated in a standby mode and activated in an active mode; a transmission unit suitable for selectively transmitting an output signal of the power-gated logic circuit to an output terminal in response to a third power gating enable signal; a clocked latch unit suitable for latching a signal of the output terminal in the standby mode and an initial stage of the active mode in response to a second power gating enable signal; and an internal circuit suitable for operating based on the signal of the output terminal, wherein the first to third power gating enable signals are sequentially activated.

Abstract: A semiconductor device includes: a power-gated logic circuit suitable for operating in response to a first power gating enable signal which is deactivated in a standby mode and activated in an active mode; a transmission unit suitable for selectively transmitting an output signal of the power-gated logic circuit to an output terminal in response to a third power gating enable signal; a clocked latch unit suitable for latching a signal of the output terminal in the standby mode and an initial stage of the active mode in response to a second power gating enable signal; and an internal circuit suitable for operating based on the signal of the output terminal, wherein the first to third power gating enable signals are sequentially activated.

Abstract: An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n? source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Abstract: In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: This invention relates to an erase circuit of flash memory device comprising an erase verifying block unit outputting a final loop signal when an chip erasing operation is not performed within a predetermined time, a high voltage detection unit outputting a high voltage signal in response to an inverted chip erase signal, a buffer outputting an output enable signal in response to an inverted output enable signal, a control unit outputting a first to third select address signals in response to said final loop signal, inverted high voltage signal and output enable signal, an address counter unit outputting data in response to said first to third select address signals, an output multiplexor outputting one of a sense amp output signal, hardware flag and data read from said address counter unit in response to said first to third select address signals, sense amp control signal and hardware flag signal.

Abstract: The present invention discloses a delay circuit which obtains constant a delay time of delay circuit using an output capacitor by making the resistance of MOS transistor lowest, at the low voltage, middle at the intermediate voltage, and largest at the high voltage, so that the delay time of delay circuit using an output capacitor is kept constant regardless of the change in power source voltage.

Abstract: The present invention relates to a flash memory device and is constructed in such a way that the memory cell blocks are sequentially selected according to the input of the erasing signal and the output voltage of the negative charge pump is supplied only to the selected memory cell block to prevent the degradation of the operational performance of the device due to excessive load applied to the output terminal of the negative charge pump at the time of erase operation. Therefore, the present invention relates to a flash memory device in which the magnitude of the load applied to the output terminal of the negative charge pump is effectively reduced and accordingly, the degradation of operational performance of the device can be prevented.

Abstract: The present invention relates to a flash memory device and, more particularly, to a flash memory device which is constructed to prevent over-erase and stress of a cell by preventing re-erase of a sector, which was confirmed as a pass, at the time of the re-erase operation due to an occurrence of a fail sector by storing the address of the sector, which was confirmed as a pass, at the time of the erase operation of a multi sector, so as to improve the reliability of the product and the life of the cell.The present invention generally applies to all the devices which utilize a multi sector erase performing algorithm among flash memory devices which utilize a stack memory cell.

Abstract: The present invention relates to a sense amplifier, and more particularly to a sense amplifier which raises the sensing current by connecting serially the transistors which are inputs to the output signal from the additional sense amplifier to the bit lines, and then turning on the transistors connected to the bit lines when the current flowing through the memory cell is lower than the expected design current value during a read-out operation.