Abstract: A buffer circuit for use in a digital communication system includes a memory and a controller coupled to the memory. The memory is configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system. The controller is operative to store data from the first data stream into corresponding timeslots in the memory in a first order, to individually adjust delays of the respective timeslots as a function of respective delay control parameters, and to generate a second data stream by reading the timeslots stored in the memory in a second order.

Abstract: Methods and apparatus are provided for modeling signal delays in a metastability protection circuit. A metastability protection circuit that processes a signal that crosses between two clock domains is modeled by introducing a random transition delay into the signal upon detection of an edge in the signal. Thereafter, an effect of the random transition delay on one or more downstream logic elements can be evaluated. The random transition delay simulates a timing effect of a metastable state. The random transition delay can optionally be introduced only during a simulation stage of the metastability protection circuit. For example, the metastability protection circuit can be defined using a Register Transfer Language and the Register Transfer Language includes one or more statements that selectively allow the introducing step.

Abstract: A buffer circuit for use in a digital communication system includes a memory and a controller coupled to the memory. The memory is configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system. The controller is operative to store data from the first data stream into corresponding timeslots in the memory in a first order, to individually adjust delays of the respective timeslots as a function of respective delay control parameters, and to generate a second data stream by reading the timeslots stored in the memory in a second order.

Abstract: A designer configurable processor for a single or multi-processing system is described. The processor includes a plurality of designer configurable computational units, such as Very Long Instruction Word (VLIW) processor task engine, that operate in parallel. A memory device communicates with the plurality of computational units through a data communication module. The memory device stores at least one of data and instruction code. A software development tool, which can include a compiler, an assembler, an instruction set simulator, or a debugging environment, configures the plurality of computational units. The software development tool configures various aspects of the processor architecture and various operating parameters of the processor and can generate a synthesizable RTL description of the processor and a single or multi-processing system.

Abstract: A method for detecting and processing synchronization marks extracted from a prerecorded wobbled groove formed in a compact disk in order to produce pseudo-sync signals using a high frequency phase locked loop servoing to the disk speed to generate the signals.

Abstract: A method for detecting and processing ATIP information extracted from a prerecorded wobbled groove formed in a compact disk is disclosed. The prerecorded wobbled groove has a plurality of blocks of information. The method includes extracting an FM signal from the wobbled groove and providing a high frequency phase-lock loop which responds to the extracted FM signal to produce a high frequency clock. The method further includes converting such FM signal into biphase data by sampling and latching the FM ATIP signal from the wobbled groove; and digitally comparing a predetermined count value to a count value derived from the high frequency clock and the FM signal. It further includes extracting a clock signal from a digital phase-lock loop responsive to the biphase data; and providing an ATIP decoder which in response to the biphase data, biphase clock, and high frequency clock signal provides sync detection and address information.