Abstract: A reference cell for a 1T-1C memory is disclosed for use in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.

Abstract: A reference cell for a IT-1C memory can be used in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.