Patents by Inventor H. C. Hsieh

H. C. Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7429501
    Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 30, 2008
    Assignee: Xilinx, Inc.
    Inventors: Paul Ying-Fung Wu, Soon-Shin Chee, Steven H. C. Hsieh
  • Patent number: 7257511
    Abstract: Disclosed is a DC thermal energy generator for heating localized regions of an integrated circuit. The integrated circuit includes a pair of static circuits whose outputs are shorted, and are in contention. Contention causes current to flow through the circuits, generating heat. Integrated-circuit temperature can be varied by turning on more or fewer thermal energy generators. The thermal resistance of a packaged integrated circuit is computed using a well-known relationship among the integrated circuit's measured temperature, power consumption, and the ambient temperature.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 14, 2007
    Assignee: Xilinx, Inc.
    Inventors: Steven H. C. Hsieh, Siuki Chan
  • Patent number: 7012326
    Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: March 14, 2006
    Assignee: Xilinx, Inc.
    Inventors: Paul Ying-Fung Wu, Soon-Shin Chee, Steven H. C. Hsieh
  • Patent number: 6895566
    Abstract: Test methods and circuits isolate thermal effects from AC effects on circuit performance. Critical paths for a failing programmable logic device (PLD) are identified and tested. This testing minimizes the impact of power-supply flicker and noise by eliminating or inactivating circuitry not required to test the critical paths. DC thermal energy generators are instantiated on the PLD adjacent the critical paths to heat the critical paths to one or more test temperatures. The critical paths are then tested over an appropriate range of temperatures and supply-voltages.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 17, 2005
    Assignee: Xilinx, Inc.
    Inventors: Siuki Chan, Steven H. C. Hsieh
  • Patent number: 6847010
    Abstract: Disclosed is a DC thermal energy generator for heating localized regions of an integrated circuit. The integrated circuit includes a pair of static circuits whose outputs are shorted, and are in contention. Contention causes current to flow through the circuits, generating heat. Integrated-circuit temperatures can be varied by turning on more or fewer thermals energy generators. The thermal resistance of a, packaged integrated circuit is computed using a well-known relationship integrated circuit's measured temperature, power consumption, and the ambient temperature.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: January 25, 2005
    Assignee: Xilinx, Inc.
    Inventors: Steven H. C. Hsieh, Siuki Chan
  • Patent number: 6564986
    Abstract: A method and assembly for testing multiple IC packages for solder joint fractures that occur in response to thermal cycling. A test PCB is fabricated with contact pads arranged to match a BGA IC package footprint, wherein pairs of the contact pads are linked by conductive traces (lines) to form a lower portion of a daisy chain. The BGA IC package is modified to link associated pairs of solder balls, e.g., using wire bonding to form an upper portion of the daisy chain. Mounting the BGA IC package on the test PCB completes the daisy chain. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked by wire bonding, the daisy chain provides a conductive path that passes through all solder balls of the BGA IC package.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: May 20, 2003
    Assignee: Xilinx, Inc.
    Inventor: Steven H. C. Hsieh
  • Patent number: 6234316
    Abstract: The invention describes a wafer protective container for holding integrated circuit (IC) wafers. The wafer protective container comprises a container body, a locking device, a container cover, and a plurality of fasteners assembled together to prevent movement of the IC wafers during transportation. The container body has at least an opening to allow easy loading and unloading of the IC wafers, while the locking device is used to keep the IC wafers in position in the container body. The container cover, which covers the container body, provides more protection for the IC wafers. The container cover has a plurality of notches to enhance ease of opening the IC wafer protective container. Since the fasteners can secure the container cover to the container body, a seal between the container cover and the container body is not broken as a result of rigorous movement during transportation, thus reducing the risk of contaminating the IC wafers.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: May 22, 2001
    Assignee: United Microelectronics Corp.
    Inventors: H. C. Hsieh, Jason Horng
  • Patent number: 5477138
    Abstract: A universal verification unit resembling certain aspects of an electronic package is used for testing the proper calibration of different lead inspection systems. Comparison of readings provided by the system when the unit is inspected to actual values will indicate whether the system is properly calibrated.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: December 19, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Scott A. Erjavic, Steven H. C. Hsieh