Patents by Inventor H.C. Jang
H.C. Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8927109Abstract: Reinforced wood flooring according to one embodiment includes: a surface layer having a plurality of wood sheets and a resin-impregnated paper sheet interposed between the wood sheets, in which each of the wood sheets has a predetermined thickness and a plate shape, and the wood sheets and the resin-impregnated paper sheets are bonded together into a unitary body through hot-pressing; an adhesive layer formed beneath the surface layer to serve as an adhesive; and a plywood arranged beneath the adhesive layer and attached to a lower side of the surface layer by the adhesive lay.Type: GrantFiled: November 22, 2010Date of Patent: January 6, 2015Assignee: LG Hausys, Ltd.Inventors: Ji Woong Kim, H. C. Jang
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Publication number: 20120315452Abstract: Reinforced wood flooring according to one embodiment includes: a surface layer having a plurality of wood sheets and a resin-impregnated paper sheet interposed between the wood sheets, in which each of the wood sheets has a predetermined thickness and a plate shape, and the wood sheets and the resin-impregnated paper sheets are bonded together into a unitary body through hot-pressing; an adhesive layer formed beneath the surface layer to serve as an adhesive; and a plywood arranged beneath the adhesive layer and attached to a lower side of the surface layer by the adhesive lay.Type: ApplicationFiled: November 22, 2010Publication date: December 13, 2012Applicant: LG HAUSYS, LTD.Inventors: Ji Woong Kim, H.C. Jang
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Publication number: 20120220091Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.Type: ApplicationFiled: March 12, 2012Publication date: August 30, 2012Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20110001189Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.Type: ApplicationFiled: September 9, 2010Publication date: January 6, 2011Inventors: Ashok Challa, J. G. Lee, J. Y. Jung, H. C. Jang
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Publication number: 20080150020Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region.Type: ApplicationFiled: January 22, 2008Publication date: June 26, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J. G. Lee, Peter H. Wilson, Joseph A. Yedinak, J. Y. Jung, H. C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20080135931Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridlay, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sanl, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20060214221Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.Type: ApplicationFiled: May 31, 2006Publication date: September 28, 2006Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter Wilson, Joseph Yedinak, J.Y. Jung, H.C. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey
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Publication number: 20050167742Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.Type: ApplicationFiled: December 29, 2004Publication date: August 4, 2005Applicant: Fairchild Semiconductor Corp.Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter Wilson, Joseph Yedinak, J.Y. Jung, H.C. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey