Abstract: A door inside release spring for a vehicle door assembly includes a torsional spring body, and a first spring arm extending from a first axial end of the spring body. The first spring arm is configured to be operably connected to an inside release lever to bias a position of the inside release lever. A second spring arm extends from a second axial end of the spring body opposite the first axial end. The second spring arm is configured to be operably connected to a child lock lever to bias a position of the child lock lever.

Abstract: A cable conduit end for securing a cable to a cable abutment of a latch is provided. The cable conduit end having: a housing; an alignment feature incorporated into a surface of the housing; a flexible retention feature integrally formed with the conduit end, wherein the flexible retention feature is spring biased away from the housing to a first position; and a radial retention feature extending outwardly away from the housing, wherein the flexible retention feature is located proximate to a first end of the housing and the radial retention feature is located proximate to a second end of the housing.

Abstract: A vehicle latch assembly includes a housing. Also included is a pawl disposed within the housing, the pawl rotatable between a first angular position and a second angular position. Further included is a bumper operatively coupled to the housing, the bumper having a conical head portion positioned for engagement with the pawl in the second angular position of the pawl.

Abstract: A cable conduit end for securing a cable to a cable abutment of a latch is provided. The cable conduit end having: a housing; an alignment feature incorporated into a surface of the housing; a flexible retention feature integrally formed with the conduit end, wherein the flexible retention feature is spring biased away from the housing to a first position; and a radial retention feature extending outwardly away from the housing, wherein the flexible retention feature is located proximate to a first end of the housing and the radial retention feature is located proximate to a second end of the housing.

Abstract: Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.

Abstract: A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.

Abstract: A cable conduit end for securing a cable to a cable abutment of a latch is provided. The cable conduit end having: a housing; an alignment feature incorporated into a surface of the housing; a flexible retention feature integrally formed with the conduit end, wherein the flexible retention feature is spring biased away from the housing to a first position; and a radial retention feature extending outwardly away from the housing, wherein the flexible retention feature is located proximate to a first end of the housing and the radial retention feature is located proximate to a second end of the housing.

Abstract: Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. A scalar factor is applied to another voltage signal that is inversely proportional to the temperature to produce a scaled voltage signal. The scaled voltage signal is converted to a second frequency-based signal, which is converted to a digital bit value, and then the two digital bit values are compared. The temperature is determined when the digital bit values substantially match.

Abstract: A component for a vehicle latch assembly is provided, the component having: an electrical sub-system having a plurality of circuit paths each being electrically connected to a common ground, the electrical sub-system being molded into a pre-mold by a first molding process, the pre-mold comprising an encapsulation layer molded around the common ground and an at least one structural member secured to the encapsulation layer and at least one of the plurality of circuit paths, the structural member providing rigidity to the pre-mold; and a plurality of locating features extending from at least one of the encapsulation layer and the structural member.

Abstract: A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.

Abstract: A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.

Abstract: A latch having: a claw configured to rotate between an unlatched position and a latched position; a pawl configured for movement between an engaged position and a disengaged position, wherein the pawl retains the claw in the latched position when the pawl is in the engaged position and wherein the pawl releases the claw when it is in a disengaged position and the claw is free to move from the latched position to the unlatched position; a bumper located on the pawl to dampen noises as the pawl is moved by a portion of the claw; and wherein the detent lever is pivotally mounted to a frame of the latch proximate to a corner of an opening of the latch.

Abstract: Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

Abstract: A driver circuit includes first and second pluralities of series-connected inverters for pre-driving an input signal to first and second drive transistors, and a plurality of capacitors. The first and second drive transistors coupled to the last inverter of the first and second pluralities of series-connected inverters. Each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters. In another embodiment, a plurality of discharge circuits is coupled to the first plurality of series-connected inverters. Another embodiment includes a combination of capacitors and discharge circuits coupled to the first plurality of series-connected inverters. The embodiments provide a driver circuit with high frequency voltage regulation.

Abstract: A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Abstract: An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.

Abstract: An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.

Abstract: Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Abstract: An IC includes: a substrate having a thick oxide portion and a thin oxide portion; a load circuit disposed on the thin oxide portion and coupled between a supply node and a virtual supply node; and a current source circuit and protection circuit disposed on the substrate. The current source circuit has an output coupled to the virtual supply node and is operable to provide a voltage at the virtual supply node. The protection circuit includes a sensing portion and a protection portion. The sensing portion is coupled to the virtual supply node and is operable to detect the voltage at the virtual supply node. The protection portion is coupled to the sensing portion and is operable, in response to the sensed voltage, to prevent a difference in voltage between the voltage at the virtual supply node and a second voltage at the supply node from exceeding a maximum voltage.