Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

Abstract: A semiconductor structure with a high-K insulative layer. An insulative layer is disposed on a silicon substrate and includes a first nitride layer and a high-K layer. A gate is disposed on the insulative layer. The insulative layer further includes sidewalls extending at least flush with corresponding sidewalls of the gate. Source and drain regions are disposed within the substrate adjacent to the insulative layer.

Abstract: A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. This is due to the fact that each material has a dielectric constant that is different. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of two spacers at the sidewalls of the gate. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacers. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.

Abstract: A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of a single spacer located within the gate at the sidewall nearest the drain of the semiconductor device. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacer and the other sidewall of the gate. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.

Abstract: Rapid thermal anneal with a gaseous dopant species is disclosed. In one embodiment, a method includes three steps. In the first step, at least one gate is formed over a semiconductor substrate. In the second step, at least one spacer for each of the gates is formed, where each spacer is adjacent to an edge of its corresponding gate. In the third step, a rapid thermal anneal with a gaseous dopant species is performed to form source and drain regions within the substrate. Desirably, the source and drain regions meet the substrate underneath the gate at shallow junctions.

Abstract: The formation of lightly doped regions under a gate of a transistor that has a reduced gate oxide is disclosed. In one embodiment, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the gate oxide is etched to reduce the length of the gate oxide. In the third step, a first ion implantation is applied, at an angle other than perpendicular to the substrate. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.

Abstract: A semiconductor fabrication process including a method of controlling the gate dielectric film thickness without adjusting the oxidation recipe. A sacrificial dielectric layer is formed on an upper surface of a semiconductor substrate. An oxidation inhibiting species is then introduced into the semiconductor substrate. The sacrificial dielectric layer is then removed from the substrate and the substrate is immersed into an oxygen bearing ambient maintained at a recipe temperature for a recipe duration. Preferably, the recipe temperature is in the range of approximately 500 to 800.degree. C. and the recipe duration is in the range of approximately 2 to 20 minutes. The final thickness of the gate dielectric film is adjusted by altering a concentration of the oxidation inhibiting species within the semiconductor substrate.

Abstract: The formation of lightly doped regions under a gate of a transistor is disclosed. In one embodiment of the invention, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the semiconductor substrate is etched. In the third step, a first ion implantation is applied. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.

Abstract: The formation of a shortage protection region is disclosed. In one embodiment, a method includes three steps. In the first step, a first ion implantation is applied to form lightly doped regions within a semiconductor substrate adjacent to sidewalls of a gate over the substrate. In the second step, two spaces are formed on the substrate, each adjacent to a sidewall of the gate, so that a second ion implantation forms heavily doped regions within the substrate adjacent to the first spacers. In the third step, two additional spacers are formed on the substrate, each overlapping and extending beyond a corresponding spacer previously formed. Thus, a third ion implantation forms lightly doped shortage protection regions within the substrate adjacent to the spacers most recently formed.