Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.

Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.