Abstract: A device for sending/receiving digital data is capable of processing different bit rates from a group of predetermined bit rates. The device may include a channel coding/decoding stage including an interleaver, a deinterleaver, and a memory whose minimum size is fixed as a function of the maximum bit rate of the group of predetermined bit rates. The memory may have a first memory space assigned to the interleaver and a second memory space assigned to the deinterleaver. The size of each of the two memory spaces may be set as a function of the bit rate actually processed by the device.

Abstract: The device for sending/receiving digital data is capable of processing different bit rates from a group of predetermined bit rates. It includes a channel coding/decoding stage including interleaving means MET and deinterleaving means MDET including a memory MM whose minimum size is fixed as a function of the maximum bit rate of said group and having a first memory space ESM1 assigned to the interleaving means and a second memory space ESM2 assigned to the deinterleaving means. The size of each of the two memory spaces is parameterable as a function of the bit rate actually processed by the device.