Abstract: Aspects of the invention include receiving data that includes a group of n symbols to be written to a plurality of storage units. The group of symbols is mapped into a codeword of n+k symbols, each assigned to one of the storage units. The codeword is configured to allow at least one of the n symbols to be reconstructed using a subset of the n+k symbols. At least one of the n+k symbols is assigned to one of the storage units based at least in part on content of the at least one of the n+k symbols. Writing each of the n+k symbols to its assigned storage unit in the plurality of storage units is initiated. The writing includes optimizing storage capacity of the assigned storage unit based at least in part on determining that the symbol has the same content as another symbol previously stored in the storage unit.

Abstract: Aspects of the invention include receiving data that includes a group of n symbols to be written to a plurality of storage units. The group of symbols is mapped into a codeword of n+k symbols, each assigned to one of the storage units. The codeword is configured to allow at least one of the n symbols to be reconstructed using a subset of the n+k symbols. At least one of the n+k symbols is assigned to one of the storage units based at least in part on content of the at least one of the n+k symbols. Writing each of the n+k symbols to its assigned storage unit in the plurality of storage units is initiated. The writing includes optimizing storage capacity of the assigned storage unit based at least in part on determining that the symbol has the same content as another symbol previously stored in the storage unit.

Abstract: Embodiments include methods, systems and computer program products for handling a distributed job by a FPGA. Aspects include obtaining a demand for performance in the distributed job and determining, according to the demand for performance, whether to reconfigure the FPGA. Aspects also include dynamically reconfiguring at least a part of the FPGA in response to determination of reconfiguring the FPGA. With the method and corresponding system, the performance of the distributed job can be effectively improved.

Abstract: A mechanism is provided in a data processing system for pipelined compression of multi-byte frames. The mechanism combines a current cycle of data in an input data stream with at least a portion of a next cycle of data in the input data stream to form a frame of data. The mechanism identifies a plurality of matches in a plurality of dictionary memories. Each match matches a portion of a given substring in the frame of data. The mechanism identifies a subset of matches from the plurality of matches that provides a best coverage of the current cycle of data. The mechanism encodes the frame of data into an encoded output data stream.

Abstract: Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.

Abstract: A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.

Abstract: Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.

Abstract: Mechanisms that provide a sealed storage in a data processing device are provided. Processors of the data processing device may operate in a hardware isolation mode which allows a process to execute in an isolated environment on a processor and associated memory thereby being protected from access by other elements of the data processing device. In addition, a hardware controlled authentication and decryption mechanism is provided that is based on a hardware core key. These two features are tied together such that authentication occurs every time the isolation mode is entered. Based on the core key, which is only accessible from the hardware when in isolation mode, a chain of trust is generated by providing authentication keys for authenticating a next piece of software in the chain, in each piece of software that must be loaded, starting with the core key.

Abstract: Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.

Abstract: Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines.

Abstract: A system comprises a memory module configured to store signed page table data and a selected processing element coupled to the memory module. The selected processing element is one of a plurality of processing elements, which together comprise a portion of a multiprocessor system. The selected processing element is configured to authenticate page table management code and, based on authenticated page table management code, to sign page table data that is subsequently stored in the memory module, and to verify signed page table data that is read from the memory module.

Abstract: A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor system that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. The design structure may specify ECC hardware circuitry that provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The design structure for the processor system may permit the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The design structure may provide for local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.

Abstract: In a first aspect, a first method is provided that includes providing a plurality of select signals and a plurality of input signals for input by a multiplexer. Each select signal is adapted to cause the multiplexer to select a different one of the plurality of input signals for output by the multiplexer when the select signal is in a first logic state. The first method further includes preventing a first of the select signals that is in the first logic state from being provided to the multiplexer until the other select signals are in a second logic state. Number other aspects are provided.

Abstract: An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.

Abstract: There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.

Abstract: A data structure and corresponding search methods are disclosed for improving the performance of table lookups. A data structure for the table is employed using a hash table with hash table entries pointing to tree fragments that are contiguous in main memory and can be efficiently loaded into a local data store or cache. Leaf nodes of the tree fragments contain indicia of a data record, or indicia of another tree fragment. The data structure and corresponding search algorithm are employed for searches based on a longest prefix match in an internet routing table.