Abstract: The present invention is of a method and apparatus for processing an image comprising a data set of size M (more generally, for determining the median of any data set of size M), comprising receiving each value of the data set as a weighted set of binary digits; adding together a first constant and binary digits of greatest weight of each value of the data set; dividing the result of the adding step by a second constant to generate a binary digit of greatest weight of a median of the data set; calculating for each value a remaining value clamp function for a next lower weight of binary digits; employing results of the calculating step to repeat adding and dividing steps for the next lower weight of binary digits to generate a binary digit of next lower weight of a median of the data set; and repeating the calculating and employing steps, if necessary, for each lower weight of binary digits of the values.

Abstract: The present invention is directed to a squib fire network including built-in testing which is able to safely and efficiently verify the proper operational status of the squib fire network. All squibs in a given squib fire network of a missile can be tested prior to launch, thereby improving the reliability of weapon deployment.

Abstract: A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.

Abstract: A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.