Abstract: A low-power phase-change memory (PCM) technology with interfacial thermoelectric heating (TEH) enhancement is provided. Embodiments described herein leverage a substantial, positive thermoelectric coefficient in PCM materials to generate additional heating or cooling at an interface with another material, enabling memory switching with a large reduction in current and power. Interfacial thermoelectric engineering is applied to a PCM cell using a special class of thermoelectric materials with large negative Seebeck coefficients (e.g., bismuth telluride (Bi2Te3), lead telluride (PbTe), lanthanum telluride (La3Te4), indium selenide (InSe), silicon-germanium (Si0.8Ge0.2)) to induce efficient heating at significantly lowered power and current.

Abstract: Aspects of the present disclosure are directed to pressure sensing. As may be implemented in accordance with one or more embodiments, an external energy field is applied to a resonant circuit having inductive conductors separated by a compressible dielectric, for wirelessly detecting pressure. Specifically, the resonant circuit is responsive to the energy field and applied pressures by operating in respective states exhibiting different resonant frequencies that are based upon pressure-related compression of the compressible dielectric. These resonant frequencies, or a change in the resonant frequencies, can be used as an indication of the pressure.

Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.

Abstract: A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanostructure and metal elements is provided.

Abstract: Provided is a phase change memory device including a graphene layer inserted between a lower electrode into which heat flows and a phase change material layer, to prevent the heat from being diffused to an outside so as to efficiently transfer the heat to the phase change material layer, and a method of fabricating the phase change memory device. The phase change memory device includes a lower electrode; an insulating layer formed to enclose the lower electrode; a graphene layer formed on the lower electrode; a phase change material layer formed on the graphene layer and the insulating layer; and an upper electrode formed on the phase change material layer. Since a phase of the phase change material layer is changed at a small amount of driving current, the phase change memory device is fabricated to have a high driving speed and a high integration.

Abstract: The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than G?DUT, where G is the gain provided by the bridge circuit transistor and ?DUT is the AC signal applied to the device under test. Experiments on graphene devices and on carbon nanotube FETs demonstrate about 10 aF resolution (graphene) and about 13 aF resolution (carbon nanotube FET) at room temperature.

Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.

Abstract: Chalcogenide-based nanowire memories are implemented using a variety of methods and devices. According to an example embodiment of the present invention, a method of manufacturing a memory circuit is implemented. The method includes depositing nanoparticles at locations on a substrate. Chalcogenide-based nanowires are created at the locations on the substrate using a vapor-liquid-solid technique. Insulating material is deposited between the chalcogenide-based nanowires. Lines are created to connect at least some of the chalcogenide-based nanowires.