Patents by Inventor H. S. Philip Wong
H. S. Philip Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220115590Abstract: A low-power phase-change memory (PCM) technology with interfacial thermoelectric heating (TEH) enhancement is provided. Embodiments described herein leverage a substantial, positive thermoelectric coefficient in PCM materials to generate additional heating or cooling at an interface with another material, enabling memory switching with a large reduction in current and power. Interfacial thermoelectric engineering is applied to a PCM cell using a special class of thermoelectric materials with large negative Seebeck coefficients (e.g., bismuth telluride (Bi2Te3), lead telluride (PbTe), lanthanum telluride (La3Te4), indium selenide (InSe), silicon-germanium (Si0.8Ge0.2)) to induce efficient heating at significantly lowered power and current.Type: ApplicationFiled: October 11, 2021Publication date: April 14, 2022Inventors: Asir Intisar Khan, Eric Pop, Raisul Islam, H.-S. Philip Wong, Kenneth E. Goodson, Mehdi Asheghi, Heungdong Kwon
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Patent number: 9848775Abstract: Aspects of the present disclosure are directed to pressure sensing. As may be implemented in accordance with one or more embodiments, an external energy field is applied to a resonant circuit having inductive conductors separated by a compressible dielectric, for wirelessly detecting pressure. Specifically, the resonant circuit is responsive to the energy field and applied pressures by operating in respective states exhibiting different resonant frequencies that are based upon pressure-related compression of the compressible dielectric. These resonant frequencies, or a change in the resonant frequencies, can be used as an indication of the pressure.Type: GrantFiled: May 22, 2014Date of Patent: December 26, 2017Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Chee-Keong Tee, Lisa Yun Chen, Zhenan Bao, Darren Lipomi, Michael V. McConnell, H. S. Philip Wong
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Patent number: 9748421Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.Type: GrantFiled: March 5, 2010Date of Patent: August 29, 2017Assignee: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITYInventors: Subhasish Mitra, Nishant P. Patil, Chung Chun Wan, H.-S. Philip Wong
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Patent number: 9593014Abstract: A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanostructure and metal elements is provided.Type: GrantFiled: September 7, 2011Date of Patent: March 14, 2017Assignees: The Board of Trustees of the Leland Stanford Junior University, The Regents of the University of CaliforniaInventors: Yang Chai, Arash Hazeghi, Kuniharu Takei, Ali Javey, H. S. Philip Wong
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Patent number: 9583702Abstract: Provided is a phase change memory device including a graphene layer inserted between a lower electrode into which heat flows and a phase change material layer, to prevent the heat from being diffused to an outside so as to efficiently transfer the heat to the phase change material layer, and a method of fabricating the phase change memory device. The phase change memory device includes a lower electrode; an insulating layer formed to enclose the lower electrode; a graphene layer formed on the lower electrode; a phase change material layer formed on the graphene layer and the insulating layer; and an upper electrode formed on the phase change material layer. Since a phase of the phase change material layer is changed at a small amount of driving current, the phase change memory device is fabricated to have a high driving speed and a high integration.Type: GrantFiled: January 29, 2016Date of Patent: February 28, 2017Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior UniversityInventors: Yongsung Kim, Chiyui Ahn, Aditya Sood, Eric Pop, H.-S. Philip Wong, Kenneth E. Goodson, Scott Fong, Seunghyun Lee, Christopher M. Neumann, Mehdi Asheghi
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Publication number: 20160276585Abstract: Provided is a phase change memory device including a graphene layer inserted between a lower electrode into which heat flows and a phase change material layer, to prevent the heat from being diffused to an outside so as to efficiently transfer the heat to the phase change material layer, and a method of fabricating the phase change memory device. The phase change memory device includes a lower electrode; an insulating layer formed to enclose the lower electrode; a graphene layer formed on the lower electrode; a phase change material layer formed on the graphene layer and the insulating layer; and an upper electrode formed on the phase change material layer. Since a phase of the phase change material layer is changed at a small amount of driving current, the phase change memory device is fabricated to have a high driving speed and a high integration.Type: ApplicationFiled: January 29, 2016Publication date: September 22, 2016Inventors: Yongsung Kim, Chiyui Ahn, Aditya Sood, Eric Pop, H.S. Philip Wong, Kenneth E. Goodson, Scott Fong, Seunghyun Lee, Christopher M. Neumann, Mehdi Asheghi
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Publication number: 20140350348Abstract: Aspects of the present disclosure are directed to pressure sensing. As may be implemented in accordance with one or more embodiments, an external energy field is applied to a resonant circuit having inductive conductors separated by a compressible dielectric, for wirelessly detecting pressure. Specifically, the resonant circuit is responsive to the energy field and applied pressures by operating in respective states exhibiting different resonant frequencies that are based upon pressure-related compression of the compressible dielectric. These resonant frequencies, or a change in the resonant frequencies, can be used as an indication of the pressure.Type: ApplicationFiled: May 22, 2014Publication date: November 27, 2014Inventors: Chee-Keong Tee, Lisa Chen, Zhenan Bao, Darren Lipomi, Michael V. McConnell, H.S. Philip Wong, Ada Shuk Yan Poon
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Patent number: 8704537Abstract: The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than G?DUT, where G is the gain provided by the bridge circuit transistor and ?DUT is the AC signal applied to the device under test. Experiments on graphene devices and on carbon nanotube FETs demonstrate about 10 aF resolution (graphene) and about 13 aF resolution (carbon nanotube FET) at room temperature.Type: GrantFiled: September 27, 2011Date of Patent: April 22, 2014Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Arash Hazeghi, Joseph A. Sulpizio, David J. K. Goldhaber, H. S. Philip Wong
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Publication number: 20130306929Abstract: A multilayer-stacked phase change memory (PCM) device is provided that includes a substrate that is electrically insulative and thermally conductive, a number (n) of PCM layers deposited on the substrate, where each PCM layer is thicker than a previous PCM layer, a number (n?1) layers of passivation layer deposited between the PCM layers, where the (n) PCM layers, and the (n?1) passivation layers form a stacked multi-layer PCM on the substrate, a first electrode deposited on a first side of the multi-layer PCM stack, and a second electrode deposited on a second side of the multi-layer PCM stack, where the first side is opposite the second side, where charge transport is decoupled by stacking the PCM layers with the pasivation layers.Type: ApplicationFiled: May 16, 2012Publication date: November 21, 2013Inventors: Jaeho Lee, John P. Reifenberg, Mehdi Asheghi, Kenneth E. Goodson, H.S. Philip Wong, SangBum Kim
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Publication number: 20130076378Abstract: The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than G?DUT, where G is the gain provided by the bridge circuit transistor and ?DUT is the AC signal applied to the device under test. Experiments on graphene devices and on carbon nanotube FETs demonstrate about 10 aF resolution (graphene) and about 13 aF resolution (carbon nanotube FET) at room temperature.Type: ApplicationFiled: September 27, 2011Publication date: March 28, 2013Inventors: Arash Hazeghi, Joseph A. Sulpizio, David J.K. Goldhaber, H.S. Philip Wong
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Publication number: 20130059134Abstract: A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanaostructure and metal elements is provided.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Inventors: Yang Chai, Arash Hazeghi, Kuniharu Takei, Ali Javey, H.S. Philip Wong
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Publication number: 20110133284Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.Type: ApplicationFiled: March 5, 2010Publication date: June 9, 2011Inventors: SUBHASISH MITRA, Nishant P. Patil, Chung Chun Wan, H.-S. Philip Wong
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Publication number: 20090122148Abstract: Imaging is carried out using multiple views (e.g., from a single monolithic device) to generate an image. According to an example embodiment, a scene is imaged using disjoint sensors beyond a designated focal plane to obtain multiple views of common points in the focal plane. For the common points, the multiple views are processed to compute a depth of field, and the computed depth of field to generate an image.Type: ApplicationFiled: September 12, 2008Publication date: May 14, 2009Inventors: Keith G. Fife, H.S. Philip Wong, Abbas El Gamal
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Patent number: 7405420Abstract: Chalcogenide-based nanowire memories are implemented using a variety of methods and devices. According to an example embodiment of the present invention, a method of manufacturing a memory circuit is implemented. The method includes depositing nanoparticles at locations on a substrate. Chalcogenide-based nanowires are created at the locations on the substrate using a vapor-liquid-solid technique. Insulating material is deposited between the chalcogenide-based nanowires. Lines are created to connect at least some of the chalcogenide-based nanowires.Type: GrantFiled: September 29, 2006Date of Patent: July 29, 2008Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: H. S. Philip Wong, Stefan Meister, SangBum Kim, Hailin Peng, Yuan Zhang, Yi Cui