Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A multistage analog-to-digital converter (ADC) having improved linearity is disclosed. The ADC in an illustrative embodiment includes a sampling circuit and a plurality of stages. A first one of the stages receives a sampled analog input signal from the sampling circuit, and each of the stages operates to generate an output corresponding to one or more bits of a digital output signal representative of the analog input signal. Each of at least a subset of the stages has associated therewith at least one amplifier circuit, e.g., an output analog residue amplifier, having at least one sampling component and at least one feedback component. The sampling component and the feedback component are periodically swapped to reduce gain error between one or more of the stages so as to provide improved linearity for the ADC.

Abstract: A multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A first stage receives the sampled analog signal as the analog input signal. Each stage provides a residue output, which is the analog input signal to a subsequent stage. The residue is the analog input signal to the stage, less the analog equivalent of the partial digital output from the stage, possibly with a gain change. A voltage range over which a sample of an analog signal can vary is defined by a lower limit and an upper limit. A lower comparator threshold is established within the voltage range. An upper comparator threshold is established within the voltage range, between the lower comparator threshold and the upper limit. The analog input to the stage is quantized based on the lower and upper comparator thresholds to generate a quantized sampled analog signal.

Abstract: A phase shifter network receives at an input node an input clock signal which does not contain higher order harmonics and generates first and second phase-shifted clock signals which are 90° apart and which have the same frequency as the input clock signal. First and second voltage comparators receive the first and second phase-shifted clock signals, respectively, and generates first and second squared clock signals, respectively, which are 90° apart and which have the same frequency as the input clock signal. A combiner combines the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.

Abstract: There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.

Abstract: A method and device for controlling the common-node output voltage of a differential buffer is disclosed. According to the invention, the common-mode output voltage of the differential buffer is controlled to a desired value by supplying a first current to the output of the differential buffer and supplying a second current to the output of the differential buffer, the second current being opposite in polarity and lower in magnitude than the first current. The common-mode output voltage of the differential buffer is sensed and an adjustment current is added to the second current to adjust the common-mode output voltage to the desired value.

Abstract: A retainer assembly for releasably securing an integrated circuit package to a circuit board for testing purposes includes an insulative plate having a central aperture which surrounds the package and captures the package leads between the plate and the circuit board with the leads in conductive engagement with respective conductive contact lands on the circuit board. Screws extending through openings in the plate and the circuit board are threadingly received in nuts secured to the underside of the circuit board to releasably secure the plate with the captured integrated circuit package to the circuit board.