Abstract: The disclosure relates to modified orthopoxvirus vectors, as well as methods of using the same for the treatment of various cancers. The disclosure provides modified orthopoxvirus vectors that exhibit various beneficial therapeutic activities, including enhanced oncolytic activity, spread of infection, immune evasion, tumor persistence, capacity for incorporation of exogenous DNA sequences and safety. The viruses we have discovered are also amenable to large scale manufacturing protocols.

Abstract: The disclosed invention provides a bridge voltage inversion circuit for vacuum gauge and a pressure gauge sensor that includes the bridge voltage inversion circuit. The bridge voltage inversion circuit for a pressure gauge includes a reference capacitance, a sensor capacitance, and a transformer including a primary winding and a secondary winding that outputs a bridge voltage. The reference capacitor is connected to a first side of the secondary winding of the transformer, and the sensor capacitor is connected to a second side of the secondary winding of the transformer. The sensor capacitor senses and responds to a pressure, and a capacitance of the sensor capacitor is at a minimum when the pressure is at vacuum. The capacitance of the sensor capacitor at vacuum is less than a capacitance of the reference capacitor.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: A pin connector receptacle for use with cable TV pin connectors is described. The receptacle has a cylindrical base that can accept a pin of a pin connector from any of four quadrants. The pin connector has a spring-loaded connection plate that grips a pin of a pin connector firmly in place against the cylindrical base.

Abstract: A multi-tap distribution box for connection to a main coaxial line carrying high frequency and alternating current power signals, the multi-tap distribution box comprising a make before break jumper that ensures that connection between first and second main line coaxial connectors in the box is not interrupted when a cover of the box is removed.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods and systems include memory devices with multiple memory cells configured to store data. The memory devices also include a cache configured to store at least a portion of the data to provide access to the at least the portion of the data without accessing the multiple memory cells. The memory devices also include control circuitry configured to receive a read command having a target address. Based on the target address, the control circuitry is configured to determine that the at least the portion of the data is present in the cache. Using the cache, the control circuitry also outputs read data from the cache without accessing the plurality of memory cells.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

Abstract: A method of providing electrical energy to a dewar containing a cryogenic liquid including introducing an insulated heat pipe, with a distal end and a proximal end, into a cryogenic dewar comprising an exterior surface. And providing a Seebeck module, with a cold junction and a hot junction. The distal end is in thermodynamic contact with a cryogenic fluid and the proximal is thermodynamically connected to the cold junction. The hot junction is thermodynamically connected to the exterior surface of the dewar, thereby producing an electrical flow in the Seebeck module. A level probe may be calibrated by taking a first capacitance reading with the dewar full, and a second capacitance reading when the cryogenic liquid level is within a calibration gap. The level probe is calibrated by utilizing the first capacitance reading and the second capacitance reading.

Abstract: Methods and systems include memory devices with multiple memory cells configured to store data. The memory devices also include a cache configured to store at least a portion of the data to provide access to the at least the portion of the data without accessing the multiple memory cells. The memory devices also include control circuitry configured to receive a read command having a target address. Based on the target address, the control circuitry is configured to determine that the at least the portion of the data is present in the cache. Using the cache, the control circuitry also outputs read data from the cache without accessing the plurality of memory cells.

Abstract: The disclosed invention provides a bridge voltage inversion circuit for vacuum gauge and a pressure gauge sensor that includes the bridge voltage inversion circuit. The bridge voltage inversion circuit for a pressure gauge includes a reference capacitance, a sensor capacitance, and a transformer including a primary winding and a secondary winding that outputs a bridge voltage. The reference capacitor is connected to a first side of the secondary winding of the transformer, and the sensor capacitor is connected to a second side of the secondary winding of the transformer. The sensor capacitor senses and responds to a pressure, and a capacitance of the sensor capacitor is at a minimum when the pressure is at vacuum. The capacitance of the sensor capacitor at vacuum is less than a capacitance of the reference capacitor.

Abstract: An apparatus includes a processor to receive a plurality of telemetry datasets from a plurality of infrastructure processing units (IPUs) in a computing infrastructure. Each of the plurality of IPUs is operably coupled to a plurality of devices having a particular device type. The plurality of telemetry datasets includes a first telemetry dataset received from a first IPU and a second telemetry dataset received from a second IPU. The processor is to store first telemetry data from the first telemetry dataset in a data store, store second telemetry data from the second telemetry dataset in the data store, and in response to receiving a telemetry data request that specifies a first identifier identifying the first IPU and a job identifier, retrieve the first telemetry data from the data store based, at least in part, on the first telemetry data being associated with the first identifier and the job identifier.

Abstract: An apparatus receives current image frame data and data relating to at least one previous image frame for an electronic display. One or more parameters related to hysteresis of transistors in the electronic display are sensed. A correlation device, such as a look-up table, receives the sensed parameter or parameters and the data relating to one or more image frames, and uses this information, at least in part, to output an appropriate compensation signal for the current image frame data. The compensated current image frame data may then be supplied to the electronic display to reduce or eliminate the effects of hysteresis on the displayed image.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.