Abstract: A dual damascene process for fabricating a semiconductor device. A dielectric layer is formed on a substrate, comprising at least one via opening therein. A trench opening is formed in the dielectric layer above the via opening and the via opening widened by in-situ etching.

Abstract: A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.

Abstract: A pixel sensor that provides image sensing under radiation or space environment is disclosed. The pixel sensor includes a readout circuit and a first reset circuit. The readout circuit converts optical image signals to electronic signals, and includes p-type transistors and an n-type photosensitive element. The first reset circuit is configured to provide a reset level for a pixel output, and also includes p-type transistors. The use of p-type transistors and n-type photosensitive element provides radiation hardness without any radiation protective enclosure.

Abstract: This invention relates to a fast mountable screw assembly for CPU heat sink, comprising a base unit, a fan unit and a heat fin unit. There are hollow bolt holes on four corners of the base unit and each bolt hole is filled with a fastener for a screw to pass through and being locked on the base unit plate. The base unit links to the heat fan unit at one side and the heat fin unit at other side, and a wind conduit is connected between the base unit and the heat fin unit. The specific design is the fastener which has a spring, and the center hole of the fastener will accept the screw. The bottom of the fastener will be punched with a special tool to be pivoted on the base unit, so the fastener is moveable but never falling off. In practice, this heat sink is easy, fast and convenient to assemble with components interchangeable to gain the greatest economical benefit.

Abstract: In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.

Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.

Abstract: An image sensor with a plurality of elements which received images and a plurality of A/D conversion elements. A connection between the A/D converter and the image elements is substantially randomly assigned to avoid fixed pattern noise.

Abstract: A method of manufacturing a semiconductor device, wherein a gate structure is formed over a substrate, an interconnect layer is formed over the gate structure and the substrate, and a cap layer is formed over the interconnect layer. The interconnect layer and the cap layer are then planarized to form a substantially planar surface. A mask layer, such as an oxide mask layer, is formed over the planarized portions of the interconnect layer, and the planarized cap layer and portions of the interconnect layer are removed by etching around the mask layer.

Abstract: A method and apparatus for performing a semiconductor process wafer drying process, the method provides a semiconductor wafer having a process surface disposed in an enclosed drying space following exposure of the process surface to water; supplying a solvent vapor to the drying space at a predetermined concentration from a solvent vapor source and at least one solvent vapor supply line; determining at least one of a solvent vapor concentration and a solvent vapor temperature in the drying space; and heating in response to the determined solvent concentration at least one of at least a portion of one of the solvent vapor source, the at least one solvent vapor supply line, and at the drying space to alter the solvent vapor concentration in the drying space.

Abstract: A method for fabricating a semiconductor product first provides an embedded semiconductor product comprising: (1) a logic region having formed therein a logic field effect transistor device; (2) a memory region having formed therein a memory field effect transistor device; and (3) a kerf region having formed therein a kerf field effect transistor device. The method also provides for measuring for the embedded semiconductor product a gate electrode linewidth for each of the logic field effect transistor device, the memory field effect transistor device and the kerf field effect transistor device. The measured gate electrode linewidths may be compared among themselves or to specified target values for purposes photoexposure process control.

Abstract: A method for quantifying a rapid immunochromatographic test includes the steps of: acquiring a digital image of a rapid immunochromatographic test with an image acquiring unit, acquiring at least one main characteristics of the digital image with a characteristics acquiring unit, calculating and quantifying the main characteristics of the digital image with a neural-network quantifying unit, and sending results of the quantification to an output unit.

Abstract: An image sensor with a plurality of elements which received images and a plurality of A/D conversion elements. A connection between the A/D converter and the image elements is substantially randomly assigned to avoid fixed pattern noise.

Abstract: A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.

Abstract: A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.

Abstract: An image sensor with a plurality of elements which received images and a plurality of A/D conversion elements. A connection between the A/D converter and the image elements is substantially randomly assigned to avoid fixed pattern noise.

Abstract: A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.

Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.

Abstract: An image sensor with a plurality of elements which received images and a plurality of A/D conversion elements. A connection between the A/D converter and the image elements is substantially randomly assigned to avoid fixed pattern noise.

Abstract: An A/D conversion system for an image sensor. The image sensor acquires image signals, and outputs them to a plurality of sample and hold circuits. The sample and hold circuits are grouped and are commonly actuated, in order to simplify the control circuit. Once the signals are in the sample and hold circuits, the next clock cycle commonly actuates a plurality of A/D converters which commonly convert all of those signals. During that same clock cycle, another set of sample and hold circuits may be actuated.