Abstract: Example implementations include a method of pre-bootup fault monitor of a LASER diode driver output, by applying a first power to a pre-bootup fault monitor device, setting a fault condition at the pre-bootup fault monitor device to a no-fault state, initiating the pre-bootup fault monitor device, determining whether a first impedance of driver output satisfies an impedance threshold, and in response to a determination that the first impedance satisfies the impedance threshold, applying a second power to the output device.

Abstract: Example implementations include a method of pre-bootup fault monitor of a LASER diode driver output, by applying a first power to a pre-bootup fault monitor device, setting a fault condition at the pre-bootup fault monitor device to a no-fault state, initiating the pre-bootup fault monitor device, determining whether a first impedance of driver output satisfies an impedance threshold, and in response to a determination that the first impedance satisfies the impedance threshold, applying a second power to the output device.

Abstract: A method and apparatus can be arranged with a correlated double sampler circuit (CDS) for processing an output signal from an imaging device such as a charge-coupled device (CCD) image sensor. The correlated double sampling (CDS) circuit is described that includes an amplifier and a reduced number of capacitors that are dynamically configured using a ping-pong architecture. The described ping-pong architecture has relaxed requirements for sampling points, minimized gain mismatch error, and offset mismatches can be easily managed. The ping-pong architecture is useful in digital imaging applications such as digital scanners, digital copiers, digital cameras, and digital camcorders, to name a few.

Abstract: Circuits, devices, and methods for enabling the digitization of scanned images with an Analog Front End (AFE) circuit. The AFE circuit includes a sampler for sampling a signal produced by an image sensor and in response generating analog image samples. The AFE circuit also includes a Programmable Gain Amplifier for generating amplified samples by amplifying the analog image samples. The AFE circuit further includes an Analog to Digital Converter for generating digitized samples from the amplified samples; and a Digital Programmable Gain Amplifier for amplifying the digitized samples which are subsequently presented to a processor for further processing of the scanned image. Accordingly, the scanned image is digitized with amplification taking place both in the analog and in the digital domain, deriving benefits from each. The AFE circuit may be calibrated in two steps, once for each of the domains.

Abstract: A method and apparatus can be arranged with a correlated double sampler circuit (CDS) for processing an output signal from an imaging device such as a charge-coupled device (CCD) image sensor. The CDS circuit includes an amplifier, a set of capacitors that are dynamically configured for sampling and holding operations, and a reduced number of capacitive digital-to-analog converter (CDAC) circuits, all arranged in a ping-pong architecture. The described ping-pong architecture is useful in digital imaging applications such as digital scanners, digital copiers, digital cameras, and digital camcorders, to name a few.

Abstract: A method and apparatus for spread spectrum clock generation is provided. Modulation of the clock signal may be accomplished with an N/N?1 clock divider. The N/N?1 clock divider is configured to divide the clock signal by N or N?1, depending on the carry output signal of an accumulator circuit. The accumulator circuit is configured to provide the carry output signal in response to a modulating waveform signal. The modulating waveform signal may be a triangle wave, a sinusoidal wave, another waveform appropriate for spread-spectrum clock generation, and the like.

Abstract: Circuits, devices and methods provide a phase delay and use it to select when an analog color signal is converted to digital. The phase delay is adjustable, which permits choosing a moment in time when conversion results in improved processing. A PLL circuit receives the synchronizing signal of the color signals, and generates phased signals. A phase adjuster generates an adjustable delay signal by mixing in suitable proportions two of the phased signals that are 45 degrees apart. The delay signal is used by an analog to digital converter, to adjust when exactly it is to be sampled.

Abstract: An analog front-end (AFE) circuit may include a correlated double sampler (CDS) with a ping-pong architecture, and a ping-pong mismatch correction circuit. The CDS employs a ping data path during ping phases, and employs a pong data path during pong phases. The ping-pong mismatch correction circuit is arranged to correct a mismatch between a gain that is associated with the ping data path and a gain that is associated with the pong data path. Further, the ping-pong mismatch correction circuit is arranged to correct a mismatch between an offset that is associated with the ping data path and an offset that is associated with the pong data path.

Abstract: A transceiver circuit includes driver circuits, receiver circuits, and suspend-mode buffers that are arranged to withstand an over-voltage conditions that would otherwise damage those circuits. An over-voltage sense circuit is arranged to detect the over-voltage condition on a data line in the transceiver. Cascode devices are placed in critical points of the various circuits, while voltages are coupled to other critical points such that none of the transistor devices that are coupled to the data lines are damaged by the over-voltage condition. Selector circuits are arranged to couple the highest detected voltages to various transistor wells to prevent forward biasing parasitic diodes in the transistors. Series switching circuits are arranged to break critical conduction paths during the over-voltage condition. The over-voltage protection scheme is suitable for use in integrated USB transceivers.

Abstract: A high-speed charge-pump circuit includes an array of current source/sinks circuits that are selectable according to UP and DOWN control signals, and a programmable setting. Each current source/sink circuit includes a current source circuit and a current sink circuit. The current source and current sink circuits are coupled to cascode circuits to minimize charge feed-through at the output of the charge-pump circuit. Matched switching circuits are configured to absorb charges that are injected at a common node between the cascode circuits and the current source/sink circuits. A clamp adjustment circuit is arranged to provide clamp voltages to the common node when the current source/sink circuits are in an off mode such that switching speeds are improved. The reduced switching-times permit the charge-pump to operate at high speeds.

Abstract: A display interface is arranged to processes analog input signals to provide digital output signals. The display interface includes a series of programmable current sources, an input buffer circuit, a first reference buffer circuit, a second reference buffer circuit, and an analog-to-digital converter. The programmable current sources are arranged to provide first and second reference signals, which are buffered by reference buffer circuits and provided to the analog-to-digital converter. The input buffer circuit provides a buffered input signal to the analog-to-digital converter, and operates in an open-loop configuration for improved operating speed. The analog-to-digital converter is configured to provide a digital output signal (DOUT) in response to the buffered input signal. The analog-to-digital converter includes gain and offset settings that are changed by adjusting the progranmnable current sources. The programmable current sources and reference buffer circuits are outside of the input signal path.

Abstract: A driver circuit in accordance with the present invention combines current controlled current source and sink circuits, which are independent of process, temperature, and supply voltage, and voltage controlled current source and sink circuits to control the slew rate at the output of the driver circuit and thereby reduce switching noise. The driver includes an output transistor coupled to an output node, a current source, a current mirror transistor having a control node connected to the control node of the output transistor and a conduction path coupled to the current source, and a voltage controlled switch coupled between the conduction path of the current mirror transistor and the control node of the output transistor. The voltage controlled switch is coupled to the output node and is open when the output node is within a first voltage range, and is closed when the output node is within a second voltage range.

Abstract: A selectively configurable analog signal sampler, e.g., for use in an imaging system, for generating a differential sampled analog output signal which corresponds to a single-ended analog input signal with one or more signal characteristics including a positive signal polarity, a negative signal polarity, a return-to-reference signal waveform and a non-return-to-reference signal waveform. A switched capacitor matrix is configured, along with an operational amplifier with differential inputs and outputs, to allow all single-ended analog input signals with such signal characteristics to be sampled and converted to corresponding differential sampled analog output signals. Additionally, an accumulation mode of operation is provided in which the signal sampler accumulates N successive samples of the input signal and outputs the sum of such N samples, thereby allowing the signal sampler to operate at its rated speed while the circuit providing the input signal, e.g., an image sensor, operates at N-times such speed.