Patents by Inventor Ha Hoang

Ha Hoang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107069
    Abstract: According to one embodiment a semiconductor device includes an oxide semiconductor column that extends in a first direction. A first electrode contacts a first end of the oxide semiconductor column and a second electrode contacts a second end. A gate electrode surrounds a portion of the oxide semiconductor column. A first insulating film is between the gate electrode and the oxide semiconductor column. A second insulating film is between the gate electrode and the first electrode in the first direction and surrounds the oxide semiconductor column via the first insulating film. A region in which at least a part of the oxide semiconductor column is accommodated is formed by the gate electrode and the second insulating film, and the region has a stepped surface facing towards the second electrode.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 27, 2025
    Inventors: Takeru MAEDA, Sakuya KANEKO, Kenichiro TORATANI, Takafumi OCHIAI, Kazuhiro MATSUO, Masaya TODA, Ha HOANG, Kotaro NODA
  • Publication number: 20250105023
    Abstract: A manufacturing method includes loading a substrate into a chamber, the substrate including oxide semiconductor; configuring a temperature in the chamber to a first temperature; supplying an oxidizing gas into the chamber; lowering the temperature in the chamber from the first temperature; stopping supplying the oxidizing gas into the chamber after lowering the temperature; and unloading the substrate from the chamber after the temperature in the chamber reaches a second temperature lower than the first temperature.
    Type: Application
    Filed: August 28, 2024
    Publication date: March 27, 2025
    Applicant: Kioxia Corporation
    Inventors: Shunichi YONEDA, Kazuhiro MATSUO, Masaya TODA, Kota TAKAHASHI, Masaya NAKATA, Kenichiro TORATANI, Ha HOANG, Takuma DOI, Wakako MORIYAMA
  • Publication number: 20240421071
    Abstract: A semiconductor memory device includes a plurality of memory layers arranged in a first direction, a first via-wiring extending in the first direction, a second via-wiring in a position different from a position of the first via-wiring in a second direction and extending in the first direction. One of the plurality of memory layers includes a first wiring disposed between the first and the second via-wiring and extending in a third direction, a first semiconductor layer electrically connected to the first via-wiring, a first gate electrode opposed to the first semiconductor layer and electrically connected to the first wiring, a first memory portion electrically connected to the first semiconductor layer, a second semiconductor layer electrically connected to the second via-wiring, a second gate electrode opposed to the second semiconductor layer and electrically connected to the first wiring, and a second memory portion electrically connected to the second semiconductor layer.
    Type: Application
    Filed: June 14, 2024
    Publication date: December 19, 2024
    Applicant: Kioxia Corporation
    Inventors: Ha HOANG, Kazuhiro MATSUO, Mutsumi OKAJIMA, Takamitsu OCHI, Tsuyoshi SUGISAKI, Isamu UJIIE
  • Publication number: 20240324170
    Abstract: A semiconductor device manufacturing method includes transferring a substrate including a structure that has a first surface at which indium is exposed, and a second surface at which a metal is exposed, to a chamber of a film forming device, supplying an indium reducing gas to the chamber at a first temperature at which indium is able to transition to a gaseous state, and supplying a film forming gas to the chamber at a second temperature higher than the first temperature to form a first film on the first surface and the second surface, after supplying the reducing gas.
    Type: Application
    Filed: February 27, 2024
    Publication date: September 26, 2024
    Inventors: Masaya TODA, Kazuhiro MATSUO, Ha HOANG, Kota TAKAHASHI, Kenichiro TORATANI, Wakako MORIYAMA
  • Patent number: 12101928
    Abstract: A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 24, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Natsuki Fukuda, Ryota Narasaki, Takashi Kurusu, Yuta Kamiya, Kazuhiro Matsuo, Shinji Mori, Shoji Honda, Takafumi Ochiai, Hiroyuki Yamashita, Junichi Kaneyama, Ha Hoang, Yuta Saito, Kota Takahashi, Tomoki Ishimaru, Kenichiro Toratani
  • Patent number: 11974432
    Abstract: According to one embodiment, a semiconductor storage device includes a plurality of electrode films on a substrate, spaced from one another in a first direction. A charge storage film is provided on a side face the electrode films via a first insulating film. A semiconductor film is provided on a side face of the charge storage film via a second insulating film. The charge storage film includes a plurality of insulator regions contacting the first insulating film, a plurality of semiconductor or conductor regions provided between the insulator regions and another insulator region.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Hiroyuki Yamashita, Yuta Saito, Keiichi Sawa, Kazuhiro Matsuo, Yuta Kamiya, Shinji Mori, Kota Takahashi, Junichi Kaneyama, Tomoki Ishimaru, Kenichiro Toratani, Ha Hoang, Shouji Honda, Takafumi Ochiai
  • Publication number: 20230402548
    Abstract: In general, according to one embodiment, a semiconductor device includes first to third conductors, a semiconductor, a first insulator, and an insulation region. The semiconductor includes a metal oxide and extends in the first direction to be in contact with the first conductor and the third conductor. The insulation region is surrounded by the semiconductor and extends in the first direction to be in contact with the first conductor. The semiconductor includes a first portion and a second portion defined between the first portion and the insulation region. A concentration of a first element contained in the metal oxide of the semiconductor is higher in the second portion than in the first portion.
    Type: Application
    Filed: November 7, 2022
    Publication date: December 14, 2023
    Applicant: Kioxia Corporation
    Inventors: Ha HOANG, Kazuhiro MATSUO, Kenichiro TORATANI
  • Publication number: 20230328957
    Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, spaced from the first electrode, and containing nitrogen (N). In addition, a first distance between the first electrode and the gate insulating layer in a first direction from the first electrode to the second electrode is smaller than a second distance between the first electrode and the gate electrode in the first direction.
    Type: Application
    Filed: September 2, 2022
    Publication date: October 12, 2023
    Applicant: Kioxia Corporation
    Inventors: Masaya TODA, Tomoki ISHIMARU, Ha HOANG, Kota TAKAHASHI, Kazuhiro MATSUO, Takafumi OCHIAI, Shoji HONDA, Kenichiro TORATANI, Kiwamu SAKUMA, Taro SHIOKAWA, Mutsumi OKAJIMA
  • Publication number: 20230290882
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and an oxide semiconductor layer provided between the first electrode and the second electrode and including a first region, a second region between the first region and the second electrode, and a third region between the first region and the second region. A gate electrode surrounds the third region, and a gate insulating layer is between the gate electrode and the third region. A first resistivity of the first region is higher than a second resistivity of the second region. A first distance between the first electrode and the gate electrode in a first direction from the first electrode toward the second electrode is shorter than a second distance between the gate electrode and the second electrode in the first direction.
    Type: Application
    Filed: August 26, 2022
    Publication date: September 14, 2023
    Inventors: Ha HOANG, Kazuhiro MATSUO, Tomoki ISHIMARU, Kenichiro TORATANI
  • Publication number: 20230200050
    Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a first insulating layer provided between the first electrode and the gate electrode; and a second insulating layer provided between the second electrode and the gate electrode. In a cross section parallel to a first direction from the first electrode to the second electrode, a first portion of the oxide semiconductor layer is provided between the gate insulating layer and the first electrode. In the cross section, a second portion of the oxide semiconductor layer is provided between the gate insulating layer and the second electrode.
    Type: Application
    Filed: June 15, 2022
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventors: Akifumi GAWASE, Ha HOANG, Atsuko SAKATA, Yuta KAMIYA, Kazuhiro MATSUO, Keiichi SAWA, Kota TAKAHASHI, Kenichiro TORATANI, Yimin LIU
  • Patent number: 11463982
    Abstract: A method is provided for geo-location of a wireless target device. The method is able to generate complete statistical information about the target device in the form of a joint probability density function of the target's location. The method includes obtaining time of arrival measurements associated with reception, at a plurality of receiver devices at known or measured locations, of one or more wireless transmissions made by a target device at a location that is unknown. Based on the time of arrival measurements, the method includes computing a joint probability density function that is descriptive of a probability that the target device is within any specified region. The method then involves applying the joint probability density function to a particular specified region to compute the probability that the location of the target device is within the particular specified region.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: October 4, 2022
    Assignee: CISCO SYSTEMS CANADA CO.
    Inventors: Joseph Eric Salt, Ha Hoang Nguyen
  • Publication number: 20220310640
    Abstract: A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: September 29, 2022
    Applicant: Kioxia Corporation
    Inventors: Natsuki FUKUDA, Ryota NARASAKI, Takashi KURUSU, Yuta KAMIYA, Kazuhiro MATSUO, Shinji MORI, Shoji HONDA, Takafumi OCHIAI, Hiroyuki YAMASHITA, Junichi KANEYAMA, Ha HOANG, Yuta SAITO, Kota TAKAHASHI, Tomoki ISHIMARU, Kenichiro TORATANI
  • Publication number: 20220302162
    Abstract: According to one embodiment, a semiconductor storage device includes a plurality of electrode films on a substrate, spaced from one another in a first direction. A charge storage film is provided on a side face the electrode films via a first insulating film. A semiconductor film is provided on a side face of the charge storage film via a second insulating film. The charge storage film includes a plurality of insulator regions contacting the first insulating film, a plurality of semiconductor or conductor regions provided between the insulator regions and another insulator region.
    Type: Application
    Filed: August 26, 2021
    Publication date: September 22, 2022
    Inventors: Hiroyuki Yamashita, Yuta Saito, Keiichi Sawa, Kazuhiro Matsuo, Yuta Kamiya, Shinji Mori, Kota Takahashi, Junichi Kaneyama, Tomoki Ishimaru, Kenichiro Toratani, Ha Hoang, Shouji Honda, Takafumi Ochiai
  • Publication number: 20220257516
    Abstract: Disclosed herein are therapeutic constructs including a delivery particle, at least one mitotic kinase inhibitor, and at least one immune checkpoint inhibitor. Also disclosed are therapeutic constructs including a mitotic kinase inhibitor, an immune checkpoint inhibitor, and a chemical linker. These therapeutic constructs cause cancer death by both therapeutic and immune effects and promote targeted delivery of more therapeutics to the surviving cancer cells in a positive feed-back loop. They enhance therapeutic index of free drugs and can be used intratumorally or systemically. This strategy can treat broad cancer types and is particular useful for cancer without obvious receptors for cancer-targeted delivery of otherwise toxic therapeutics.
    Type: Application
    Filed: July 13, 2020
    Publication date: August 18, 2022
    Applicants: Oregon Health & Science University, PDX Pharmaceuticals, Inc.
    Inventors: Wassana Yantasee, Moataz Reda, Worapol Ngamcherdtrakul, Ngoc Ha Hoang
  • Patent number: 11362700
    Abstract: An apparatus comprises a frequency accumulator to produce a frequency ramp, and a symbol modulator to receive symbols and to add to the frequency ramp frequency offsets representative of the symbols, to produce a modulated frequency ramp for a modulated chirp. The apparatus includes a spreading factor controller to control a roll-over rate of the modulated frequency ramp responsive to spreading factor and frequency bandwidth control signals, to control a spreading factor and a frequency bandwidth of the modulated chirp. The apparatus includes a center frequency controller to control a center frequency of the modulated frequency ramp responsive to a center frequency control signal. The apparatus includes a phase accumulator to accumulate frequency samples of the modulated frequency ramp to produce phase samples corresponding to the modulated chirp, and a vector rotator to rotate the phase samples based on an input vector to produce a modulated chirp.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 14, 2022
    Assignee: CISCO SYSTEMS CANADA CO.
    Inventors: Tung Trong Nguyen, Ha Hoang Nguyen
  • Publication number: 20210212015
    Abstract: A method is provided for geo-location of a wireless target device. The method is able to generate complete statistical information about the target device in the form of a joint probability density function of the target's location. The method includes obtaining time of arrival measurements associated with reception, at a plurality of receiver devices at known or measured locations, of one or more wireless transmissions made by a target device at a location that is unknown. Based on the time of arrival measurements, the method includes computing a joint probability density function that is descriptive of a probability that the target device is within any specified region. The method then involves applying the joint probability density function to a particular specified region to compute the probability that the location of the target device is within the particular specified region.
    Type: Application
    Filed: October 12, 2020
    Publication date: July 8, 2021
    Inventors: Joseph Eric Salt, Ha Hoang Nguyen
  • Patent number: 11005525
    Abstract: A transmitter stores mappings of distinct values of an information signal to corresponding ones of distinct combinations of K chirps taken from M chirps that are different from each other, such that each of the distinct values is mapped to a corresponding one of the distinct combinations of K chirps. The transmitter receives a distinct value among the distinct values of the information signal. The transmitter selects, based on the mappings, a distinct combination of K chirps among the distinct combinations of K chirps that is mapped to the distinct value. The transmitter sums the K chirps of the distinct combination of K chirps to produce a symbol that represents the distinct value. The transmitter modulates the symbol to produce a modulated symbol, and transmits the modulated symbol. A receiver receives a modulated symbol that conveys a distinct value, and recovers the distinct value using stored mappings.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 11, 2021
    Assignee: CISCO SYSTEMS CANADA CO.
    Inventors: Muhammad Hanif, Ha Hoang Nguyen
  • Publication number: 20210111750
    Abstract: An apparatus comprises a frequency accumulator to produce a frequency ramp, and a symbol modulator to receive symbols and to add to the frequency ramp frequency offsets representative of the symbols, to produce a modulated frequency ramp for a modulated chirp. The apparatus includes a spreading factor controller to control a roll-over rate of the modulated frequency ramp responsive to spreading factor and frequency bandwidth control signals, to control a spreading factor and a frequency bandwidth of the modulated chirp. The apparatus includes a center frequency controller to control a center frequency of the modulated frequency ramp responsive to a center frequency control signal. The apparatus includes a phase accumulator to accumulate frequency samples of the modulated frequency ramp to produce phase samples corresponding to the modulated chirp, and a vector rotator to rotate the phase samples based on an input vector to produce a modulated chirp.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Tung Trong Nguyen, Ha Hoang Nguyen
  • Patent number: 10938440
    Abstract: An apparatus comprises a frequency accumulator to produce a frequency ramp, and a symbol modulator to receive symbols and to add to the frequency ramp frequency offsets representative of the symbols, to produce a modulated frequency ramp for a modulated chirp. The apparatus includes a spreading factor controller to control a roll-over rate of the modulated frequency ramp responsive to spreading factor and frequency bandwidth control signals, to control a spreading factor and a frequency bandwidth of the modulated chirp. The apparatus includes a center frequency controller to control a center frequency of the modulated frequency ramp responsive to a center frequency control signal. The apparatus includes a phase accumulator to accumulate frequency samples of the modulated frequency ramp to produce phase samples corresponding to the modulated chirp, and a vector rotator to rotate the phase samples based on an input vector to produce a modulated chirp.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 2, 2021
    Assignee: Cisco Systems Canada Co.
    Inventors: Tung Trong Nguyen, Ha Hoang Nguyen
  • Publication number: 20200358475
    Abstract: A transmitter stores mappings of distinct values of an information signal to corresponding ones of distinct combinations of K chirps taken from M chirps that are different from each other, such that each of the distinct values is mapped to a corresponding one of the distinct combinations of K chirps. The transmitter receives a distinct value among the distinct values of the information signal. The transmitter selects, based on the mappings, a distinct combination of K chirps among the distinct combinations of K chirps that is mapped to the distinct value. The transmitter sums the K chirps of the distinct combination of K chirps to produce a symbol that represents the distinct value. The transmitter modulates the symbol to produce a modulated symbol, and transmits the modulated symbol. A receiver receives a modulated symbol that conveys a distinct value, and recovers the distinct value using stored mappings.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Inventors: Muhammad Hanif, Ha Hoang Nguyen