Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.

Abstract: An apparatus and method for generating a small-size spread spectrum clock signal that can include generating a reference clock signal by dividing an external clock signal, detecting frequency and phase differences between a reference clock signal and a comparison clock signal as error signals, modulating a controlled voltage corresponding to the current in accordance with a modulation control signal, outputting an oscillation clock signal having a frequency oscillated according to the modulated controlled voltage as a spectrum-spread version of the external clock signal, and generating the comparison clock signal by dividing the oscillation clock signal, and then compensating for the modulation of the controlled voltage in accordance with a demodulation magnitude that is generated for use in compensating for the modulation magnitude.

Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (VCO), frequency divider, phase frequency detector (PFD), charge pump, waveform generator, loop filter, switching circuit, and lock detector. The VCO generates an oscillation signal. The frequency divider multiplies the frequency of the oscillation signal. The PFD compares the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal. The charge pump generates a signal according to the error signal. The loop filter controls the VCO to modulate the frequency of the oscillation signal and generate a spread spectrum clock based on the signal of the charge pump or waveform generator. The lock detector controls the switching circuit to selectively connect the charge pump to the loop filter during a non-lock state and the waveform generator to the loop filter during a lock state.

Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (VCO), frequency divider, phase frequency detector (PFD), charge pump, waveform generator, loop filter, switching circuit, and lock detector. The VCO generates an oscillation signal. The frequency divider multiplies the frequency of the oscillation signal. The PFD compares the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal. The charge pump generates a signal according to the error signal. The loop filter controls the VCO to modulate the frequency of the oscillation signal and generate a spread spectrum clock based on the signal of the charge pump or waveform generator. The lock detector controls the switching circuit to selectively connect the charge pump to the loop filter during a non-lock state and the waveform generator to the loop filter during a lock state.

Abstract: An apparatus and method for generating a small-size spread spectrum clock signal that can include generating a reference clock signal by dividing an external clock signal, detecting frequency and phase differences between a reference clock signal and a comparison clock signal as error signals, modulating a controlled voltage corresponding to the current in accordance with a modulation control signal, outputting an oscillation clock signal having a frequency oscillated according to the modulated controlled voltage as a spectrum-spread version of the external clock signal, and generating the comparison clock signal by dividing the oscillation clock signal, and then compensating for the modulation of the controlled voltage in accordance with a demodulation magnitude that is generated for use in compensating for the modulation magnitude.

Abstract: Reset signal generators for a frequency-phase detector include a first signal source circuit is coupled to a pump-up signal of the frequency-phase detector. The first signal source circuit includes a first load therein establishing a voltage level at a first node when a first current flows through the first load. The first signal source circuit is configured to activate the first current responsive to the pump-up signal. A second signal source circuit is coupled to a pump-down signal of the frequency-phase detector. The second signal source circuit includes a second load therein establishing a voltage level at a second node when a second current flows through the second load. The second signal source circuit is configured to activate the second current responsive to the pump-down signal. A logic circuit is configured to generate the reset signal responsive to the voltage levels at the first node and at the second node.

Abstract: Reset signal generators for a frequency-phase detector include a first signal source circuit is coupled to a pump-up signal of the frequency-phase detector. The first signal source circuit includes a first load therein establishing a voltage level at a first node when a first current flows through the first load. The first signal source circuit is configured to activate the first current responsive to the pump-up signal. A second signal source circuit is coupled to a pump-down signal of the frequency-phase detector. The second signal source circuit includes a second load therein establishing a voltage level at a second node when a second current flows through the second load. The second signal source circuit is configured to activate the second current responsive to the pump-down signal. A logic circuit is configured to generate the reset signal responsive to the voltage levels at the first node and at the second node.