Patents by Inventor Ha-Min HWANG

Ha-Min HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973035
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Min Hwang, Jong Soo Kim, Ju-Young Lim, Won Seok Cho
  • Publication number: 20230253329
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Ha-Min HWANG, Jong Soo KIM, Ju-Young LIM, Won Seok CHO
  • Patent number: 11652056
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Min Hwang, Jong Soo Kim, Ju-Young Lim, Won Seok Cho
  • Publication number: 20220223525
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Application
    Filed: September 29, 2021
    Publication date: July 14, 2022
    Inventors: Ha-Min HWANG, Jong Soo KIM, Ju-Young LIM, Won Seok CHO