Abstract: An integrated circuit includes a reset control circuit suitable for outputting a reset signal when one of a first voltage and a second voltage has lower level than a reference level, and a reset execution circuit suitable for resetting a peripheral circuit based on the reset signal.

Abstract: An integrated circuit includes a reset control circuit suitable for outputting a reset signal when one of a first voltage and a second voltage has lower level than a reference level, and a reset execution circuit suitable for resetting a peripheral circuit based on the reset signal.

Abstract: A semiconductor integrated circuit includes a driving unit, a first current path and a second current path. The driving unit applies a power supply voltage to a drive node in response to a control signal. The first current path couples the drive node and an output node. The second current path couples the drive node and the output node. The first current path and the second current path are coupled in parallel between the drive node and the output node.

Abstract: A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

Abstract: A circuit for generating a power-up signal in a semiconductor memory device which can remove instability due to non-generation of a back bias voltage by detecting the back bias voltage of a memory cell internally generated when an external power voltage is applied, and detecting the external power voltage when the back bias voltage reaches a predetermined level, and which can improve the stability of the power-up signal by initializing an external power voltage detecting unit by using an initial start-up circuit.

Abstract: A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

Abstract: A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

Abstract: A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

Abstract: A circuit for generating a power-up signal in a semiconductor memory device which can remove instability due to non-generation of a back bias voltage by detecting the back bias voltage of a memory cell internally generated when an external power voltage is applied, and detecting the external power voltage when the back bias voltage reaches a predetermined level, and which can improve the stability of the power-up signal by initializing an external power voltage detecting unit by using an initial start-up circuit.

Abstract: A substrate voltage detection control circuit is disclosed. The circuit includes a substrate voltage detector detecting a substrate voltage from a charge pump, and a control circuit separately operating the substrate voltage detector in accordance with an operation mode of a chip, for thereby sensitively reacting to the variation of the substrate voltage by turning on a substrate voltage detector in the active mode.

Abstract: A back bias voltage level sensing circuit includes a constant current generation unit for generating a constant current regardless of a variation in a power supply voltage; a switch for transferring or disconnecting the constant current generated from the constant current generation unit under the control of a switch control signal; a current distribution unit for distributing the constant current transferred by the switch by using a current mirror under the control of a first control signal; a switching current removal unit for flowing the switching current generated when the switch is turned on and turned off to the ground according to a second control signal; a back bias voltage level sensing unit for sensing a level of a back bias voltage and outputting an output signal according to the current distributed by the current distribution unit; and a switching controlling unit for receiving an oscillating signal and the output signal from the back bias voltage level sensing unit and outputting a switch control

Abstract: An input buffer circuit includes a transition detecting unit for receiving an input signal, detecting a transition of the input signal, and outputting a detecting signal and a delayed input signal; a detecting signal summing unit for summing up the detecting signal and other detecting signals outputted from other transition detecting units, and outputting a plurality of summed signals; a buffer unit for transmitting the delayed input signal in accordance with the plurality of summed signals; a control signal generator for receiving one of the plurality of summed signals and a first control signal, and outputting a second control signal and a third control signal; and a write driver 204 for receiving the second and third control signals, and transmitting an output signal of the buffer unit to a cell by a trigger of the plurality of summed signals.

Abstract: A data read circuit of a memory includes an inverting unit, a precharging unit, a first amplifying unit, a second amplifying unit, and an output buffer unit. The inverting unit inverts data from a sense amplifier, and the precharging unit precharges a data bus line to Vcc/2. The first amplifying unit receives and amplifies the inverted data, and the second amplifying unit is commonly connected to an input terminal of the first amplifying unit to receive and amplify the signal output from the inverting unit. The output buffer unit receives, inverts and outputs the signal amplified by the first and second amplifying units.