Abstract: A temperature sensor system includes two P-type bipolar junction transistors (BJTs) configured as diodes and current sources operating the diodes at different current densities. The system includes a voltage reference, a multiplexer, a voltage ramp generating circuit, a comparator, an XOR circuit, a counter, and a second logic circuit (math unit). The sensor system measures temperatures by comparing the various voltages with the ramp voltage. The counter is enabled by performing an XOR function on a Start signal and the counter output or by performing an XOR function on outputs of multiple counters.

Abstract: An electronic medical record (EMR) analysis machine automatically clusters electronic medical records to produce an initial EMR analysis model and to identify high-value EMR documents such that human analysts can focus effort on labeling only high-value EMR documents to iteratively and extremely efficiently train an EMR analysis model. High-value sample EMR documents are identified as those whose membership in one or more clusters is most ambiguous, i.e., nearest the cluster boundary.

Abstract: A master-slave flip-flop includes a first latch, a second latch and a tristate driver. The first latch has a combined input/output that is coupled with a common node, a pm output, and an nm output. The tristate driver has pm and nm inputs coupled with the pm and nm outputs of the first latch, and a tristate output coupled with the common node. A pm input signal prevents the tristate driver from pulling the common node high, and an nm input signal prevents the tristate driver from pulling the common node low. The second latch is directly coupled with the common node. The first latch generates an nm signal and a pm signal in response to a signal on the first latch clk input and a state of the common node, wherein the pm signal and the nm signal have opposite polarities when the signal on the first latch clk input has a first value, and equal polarities when the signal on the first latch clk input has a second value.

Abstract: An electronic medical record (EMR) analysis machine automatically clusters electronic medical records to produce an initial EMR analysis model and to identify high-value EMR documents such that human analysts can focus effort on labeling only high-value EMR documents to iteratively and extremely efficiently train an EMR analysis model. High-value sample EMR documents are identified as those whose membership in one or more clusters is most ambiguous, i.e., nearest the cluster boundary.

Abstract: A method and apparatus for calibrating a temperature sensor is disclosed. In one embodiment, a method comprises generating first and second digital values based respectively on first and second voltages applied to a portion of a temperature sensor circuit. An arithmetic circuit may derive the value of the second voltage based on the first and second digital values. The method further comprises determining an initial value of a constant based on values of the first and second voltages, and determining a final value of the constant based on the initial voltage and at least one voltage offset. The constant may then be used in determining temperature readings for the temperature sensor.

Abstract: Window or curtain wall assemblies and concealed window fastening assemblies are disclosed. Each window panel includes two layers of glass or other material separated by a spacing mullion, which lines the perimeter of the window panel to create a sealed chamber. The depth of the sealed chamber between the two layers is variable to accommodate either thermal requirements, vertical and horizontal structural loads, or both. The chamber reduces heat loss due to convection allowing it to outperform current double or triple glazing window walls. Each chamber can connect through tubes to allow for air or gas transfer to enhance thermal performance and create the potential for other functional and aesthetic effects. When the window panels are assembled, the latching mechanism structurally unifies each panel to become a single monolithic surface that can also account for thermal expansion.

Abstract: A method and apparatus for calibrating a temperature sensor is disclosed. In one embodiment, a method comprises generating first and second digital values based respectively on first and second voltages applied to a portion of a temperature sensor circuit. An arithmetic circuit may derive the value of the second voltage based on the first and second digital values. The method further comprises determining an initial value of a constant based on values of the first and second voltages, and determining a final value of the constant based on the initial voltage and at least one voltage offset. The constant may then be used in determining temperature readings for the temperature sensor.

Abstract: Embodiments of a temperature sensing apparatus are disclosed. The apparatus may include a voltage generator and circuitry. The voltage generator may generate a first voltage level and a second voltage level dependent on an operating temperature. In response to a given change in the operating temperature, the first and second voltage levels may change, with the second voltage level changing by a different amount than the first voltage level. The voltage generator may generate a third voltage level. The circuitry may measure the first voltage level, the second voltage level, and the third voltage level, and may calculate the operating temperature dependent on a ratio of a difference between the first voltage level and the second voltage level and the third voltage level.

Abstract: Window or curtain wall assemblies and concealed window fastening assemblies are disclosed. Each window panel includes two layers of glass or other material separated by a spacing mullion, which lines the perimeter of the window panel to create a sealed chamber. The depth of the sealed chamber between the two layers is variable to accommodate either thermal requirements, vertical and horizontal structural loads, or both. The chamber reduces heat loss due to convection allowing it to outperform current double or triple glazing window walls. Each chamber can connect through tubes to allow for air or gas transfer to enhance thermal performance and create the potential for other functional and aesthetic effects. When the window panels are assembled, the latching mechanism structurally unifies each panel to become a single monolithic surface that can also account for thermal expansion.

Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.

Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.

Abstract: Embodiments of a temperature sensing apparatus are disclosed. The apparatus may include a voltage generator and circuitry. The voltage generator may generate a first voltage level and a second voltage level dependent on an operating temperature. In response to a given change in the operating temperature, the first and second voltage levels may change, with the second voltage level changing by a different amount than the first voltage level. The voltage generator may generate a third voltage level. The circuitry may measure the first voltage level, the second voltage level, and the third voltage level, and may calculate the operating temperature dependent on a ratio of a difference between the first voltage level and the second voltage level and the third voltage level.

Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes pull-up and pull-down circuits each coupled to a data input and configured to be activated responsive to a clock signal transition from a first phase to a second phase, depending on the input data. A write circuit is configured to write data into a latch of the flip-flop responsive to activation of one of the pull-up and pull-down circuits. An output driver circuit includes a dynamic portion and a static portion, with the dynamic portion being activated responsive to activation of one of the pull-up and pull-down circuits. Activation of the dynamic portion may occur concurrently with writing of the data into the latch. The output driver circuit also includes a static portion. After the clock transitions back to the first phase, the static portion may drive and hold the output while the dynamic portion is deactivated.

Abstract: A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.

Abstract: A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.

Abstract: A curable ester resin composition including (a) an ester resin; (b) at least one copolymerizable reactive monomer; and (c) an amphiphilic block copolymer containing at least one ester resin miscible block segment and at least one ester resin immiscible block segment; such that when the ester resin composition is cured, the toughness of the resulting cured ester resin composition is increased.