Patents by Inventor Ha Soo Kim

Ha Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155140
    Abstract: The present invention relates to an image information decoding method. The decoding method includes receiving a bit stream including a Network Abstraction Layer (NAL) unit that includes information related to encoded image, and parsing a NAL unit header of the NAL unit. The NAL unit header may not include 1 bit flag information that represents whether a picture is a non-reference picture or a reference picture in the entire bit stream during encoding.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jung Won Kang, Ha Hyun Lee, Jin Soo Choi, Jin Woong Kim
  • Publication number: 20240155110
    Abstract: The present invention relates to an image encoding method and an image decoding method. The image decoding method includes partitioning a picture into a plurality of coding units, constructing a coding unit group including at least one coding unit of the plurality of coding units, obtaining coding information in units of one coding unit group, and decoding at least one coding unit of the plurality of coding units included in the coding unit group by using the obtained coding information.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jung Won KANG, Sung Chang LIM, Hyun Suk KO, Ha Hyun LEE, Jin Ho LEE, Dong San JUN, Seung Hyun CHO, Hui Yong KIM, Jin Soo CHOI
  • Publication number: 20240155150
    Abstract: The present invention relates to a method for encoding and decoding an image. The method for decoding an image includes: deriving an initial motion vector from a merge candidate list of a current block; deriving a refined motion vector using the initial motion vector; and generating a prediction block of the current block using the refined motion vector.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Ha Hyun LEE, Jung Won KANG, Hyun Suk KO, Sung Chang LIM, Jin Ho LEE, Dong San JUN, Seung Hyun CHO, Hui Yong KIM, Jin Soo CHOI
  • Patent number: 11979573
    Abstract: Disclosed are a method for determining a color difference component quantization parameter and a device using the method. Method for decoding an image can comprise the steps of: decoding a color difference component quantization parameter offset on the basis of size information of a transform unit; and calculating a color difference component quantization parameter index on the basis of the decoded color difference component quantization parameter offset. Therefore, the present invention enables effective quantization by applying different color difference component quantization parameters according to the size of the transform unit when executing the quantization.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: May 7, 2024
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Sung Chang Lim, Hui Yong Kim, Se Yoon Jeong, Jong Ho Kim, Ha Hyun Lee, Jin Ho Lee, Jin Soo Choi, Jin Woong Kim
  • Patent number: 11973035
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Min Hwang, Jong Soo Kim, Ju-Young Lim, Won Seok Cho
  • Patent number: 11962803
    Abstract: The multi sample prediction method of the present invention comprises the steps of: determining a sample group consisting of a plurality of samples inside a decoding target block; determining a representative position corresponding to the sample group, inside the decoding target block; determining a representative prediction value for the sample group, on the basis of the determined representative position; and determining the determined representative prediction value as the final prediction value for each of the plurality of samples making up the sample group. The present invention enhances efficiency in encoding/decoding and reduces complexity thereof.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: April 16, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Ho Lee, Hui Yong Kim, Sung Chang Lim, Jong Ho Kim, Ha Hyun Lee, Jin Soo Choi, Jin Woong Kim
  • Publication number: 20240121385
    Abstract: The present invention relates to an intra prediction method and apparatus. The image decoding method according to the present invention may comprise decoding information on intra prediction; and generating a prediction block by performing intra prediction for a current block based on the information on intra prediction. The information on intra prediction may include information on an intra prediction mode, and the intra prediction mode may include a curved intra prediction mode.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Hyun Suk KO, Jin Ho LEE, Sung Chang LIM, Jung Won KANG, Ha Hyun LEE, Dong San JUN, Seung Hyun CHO, Hui Yong KIM, Jin Soo CHOI
  • Patent number: 11949890
    Abstract: The present invention relates to a decoding method for a bit stream that supports a plurality of layers. The decoding method may include receiving information on a set of video parameters that includes information on the plurality of layers, and parsing the set of video parameters to grasp information on the layers in the bit stream.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: April 2, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung Won Kang, Ha Hyun Lee, Jin Soo Choi, Jin Woong Kim
  • Publication number: 20240107002
    Abstract: A method for coding image information includes generating prediction information by predicting information on a current coding unit, and determining whether the information on the current coding unit is the same as the prediction information. When the information on the current coding unit is the same as the prediction information, a flag indicating that the information on the current coding unit is the same as the prediction information is coded and transmitted. When the information on the current coding unit is not the same as the prediction information, a flag indicating that the information on the current coding unit is not the same as the prediction information and the information on the current coding unit are coded and transmitted.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Applicants: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Se Yoon JEONG, Hui Yong KIM, Sung Chang LIM, Jin Ho LEE, Ha Hyun LEE, Jong Ho KIM, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Gwang Hoon PARK, Kyung Yong KIM, Tae Ryong KIM, Han Soo LEE
  • Publication number: 20240098311
    Abstract: The present invention relates to an image encoding/decoding method and apparatus. An image encoding method according to the present invention may comprise generating a transform block by performing at least one of transform and quantization; grouping at least one coefficient included in the transform block into at least one coefficient group (CG); scanning at least one coefficient included in the coefficient group; and encoding the at least one coefficient.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 21, 2024
    Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY ACADEMY COOPERATION FOUNDATION OF SEJONG UNIVERSITY
    Inventors: Sung Chang LIM, Jung Won KANG, Hyun Suk KO, Jin Ho LEE, Dong San JUN, Ha Hyun LEE, Seung Hyun CHO, Hui Yong KIM, Jin Soo CHOI, Yung Lyul LEE, Jun Woo CHOI
  • Patent number: 11936853
    Abstract: The present invention relates to an image encoding method and an image decoding method. The image decoding method includes partitioning a picture into a plurality of coding units, constructing a coding unit group including at least one coding unit of the plurality of coding units, obtaining coding information in units of one coding unit group, and decoding at least one coding unit of the plurality of coding units included in the coding unit group by using the obtained coding information.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: March 19, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung Won Kang, Sung Chang Lim, Hyun Suk Ko, Ha Hyun Lee, Jin Ho Lee, Dong San Jun, Seung Hyun Cho, Hui Yong Kim, Jin Soo Choi
  • Publication number: 20240073416
    Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, Universily-lndustry Cooperation Group of Kyung Hee University
    Inventors: Sung Chang LIM, Ha Hyun LEE, Se Yoon JEONG, Hui Yong KIM, Suk Hee CHO, Jong Ho KIM, Jin Ho LEE, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Dong Gyu SIM, Seoung Jun OH, Gwang Hoon PARK, Sea Nae PARK, Chan Woong JEON
  • Patent number: 11917170
    Abstract: The present invention relates to an image information decoding method. The decoding method includes receiving a bit stream including a Network Abstraction Layer (NAL) unit that includes information related to encoded image, and parsing a NAL unit header of the NAL unit. The NAL unit header may not include 1 bit flag information that represents whether a picture is a non-reference picture or a reference picture in the entire bit stream during encoding.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: February 27, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung Won Kang, Ha Hyun Lee, Jin Soo Choi, Jin Woong Kim
  • Patent number: 9570118
    Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 14, 2017
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Winston Lee, Ha Soo Kim
  • Patent number: 9221297
    Abstract: Disclosed are a dual surface-treated injection molding article, which is manufactured by dually surface-treating an injection molding substrate formed of a light-transmissive semi-transparent or transparent material in such a manner that a metallic appearance is expressed or any of a logo, a pattern, an ornamental design, and a picture is formed on each of inner and outer surfaces of the injection molding substrate, and a method of manufacturing the same.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Soon Shin, Jong-Bae Park, Young-Jik Lee, Hyon-Myong Song, Ha-Soo Kim
  • Patent number: 9218856
    Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 22, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Winston Lee, Ha Soo Kim
  • Publication number: 20140071782
    Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 13, 2014
    Applicant: Marvell International Ltd.
    Inventors: Winston Lee, Ha Soo Kim
  • Patent number: 8605534
    Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: December 10, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Winston Lee, Ha Soo Kim
  • Publication number: 20110253412
    Abstract: Disclosed are a dual surface-treated injection molding article, which is manufactured by dually surface-treating an injection molding substrate formed of a light-transmissive semi-transparent or transparent material in such a manner that a metallic appearance is expressed or any of a logo, a pattern, an ornamental design, and a picture is formed on each of inner and outer surfaces of the injection molding substrate, and a method of manufacturing the same.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 20, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Soon SHIN, Jong-Bae PARK, Young-Jik LEE, Hyon-Myong SONG, Ha-Soo KIM
  • Publication number: 20110058439
    Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 10, 2011
    Inventors: Winston LEE, Ha Soo KIM