Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.

Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Abstract: Provided are an electrostatic discharge (ESD) device and method of fabricating the same where the ESD device is configured to prevent electrostatic discharge which can be a cause to product failure. More particularly, the ESD device provided includes a Zener diode and a plurality of PN diodes by improving the architecture of an area wherein a Zener diode is configured compared to alternatives, to provide improved functionality when protecting against ESD events.

Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.

Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.

Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.

Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

Abstract: Provided are an electrostatic discharge (ESD) device and method of fabricating the same where the ESD device is configured to prevent electrostatic discharge which can be a cause to product failure. More particularly, the ESD device provided includes a Zener diode and a plurality of PN diodes by improving the architecture of an area wherein a Zener diode is configured compared to alternatives, to provide improved functionality when protecting against ESD events.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.