Abstract: A system and method used in a Reed-Solomon (RS) decoder for determining roots of error locator polynomials in which a first pre-computation operation is performed to obtain a p-bit polynomial solution value in a first clock cycle and second parallel feedback logical operations are performed to obtain a p-bit polynomial solution value in each subsequent clock cycles. The system excludes constant Galois Field multipliers from the critical timing path of the system so as to facilitate high speed error-locator polynomial root determination. In the case of an unshortened RS(m,d) decoder defined over the Galois Field GF(2p) where GF(2p) is a finite field of 2p elements and m=2p−1, final root location values are obtained in m cycles. In the case of a shortened RS(n,d) decoder defined over the Galois Field GF(2p) where GF(2p) is a finite field of 2p elements and m=2p−1 and n<m, final root location values are obtained in n cycles.

Abstract: An extended symbol Galois field error correcting device is provided. The device includes a singly-extended Reed-Solomon encoder configured to generate an encoded codeword, {tilde over (c)}(x). The device also includes a channel medium that is signal coupled with the singly-extended Reed-Solomon encoder. The channel medium is configured to receive the encoded codeword, {tilde over (c)}(x), and output a received input codeword, {tilde over (r)}(x). The channel medium is capable of introducing error, {tilde over (e)}(x), to the encoded codeword, {tilde over (c)}(x). The device further includes a singly-extended Reed-Solomon decoder that is coupled with the channel medium. The singly-extended Reed-Solomon decoder is configured to receive the received input codeword, {tilde over (r)}(x). The singly-extended Reed-Solomon decoder has error detection circuitry and extended symbol correction circuitry.

Abstract: The present invention is a 2.sup.n -bit serial multiplier design optimized for both speed and silicon area. The multiplier design includes source registers, recursive multiplication logic, and destination registers. According to the method of the present invention, the 2.sup.n -bit serial multiplier design is implemented by performing a precomputing (cycle-stealing) step in which source registers are preloaded with the recursively reconstructed and zero-padded input data and the designation registers are preloaded with zeros or the highest input field coefficient while the first cycle of the multiplication phase is taking place.

Abstract: A built-in self-test circuitry includes a design under test and a self-test processor. Included within the design under test is a plurality of scan row registers. The self-test processor includes a command processing section and a signal generating section. The command processing section receives information which indicates the configuration of the scan row registers. The signal generating section generates control signals which control the built-in self-testing of the circuit. The control signals are based on the information received by the command processing section. In the preferred embodiment, the command processing section includes a shift section, a load section, and a signature section. The shift section receives information which indicates a number of bits in each scan row register. The load section receives information which indicates a number of loads into the scan row registers.