Patents by Inventor Hacene Lahreche
Hacene Lahreche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8431964Abstract: The disclosure relates to electronic devices and associated methods of manufacture including materials of the Group III/N. An exemplary device successively includes, from its base towards its surface: (i) a support substrate, (ii) a layer adapted to contain an electron gas, (iii) a barrier layer, and (iv) a superficial layer extending on at least one part of the surface of the barrier layer, wherein the superficial layer has an electrical field of which the current is controlled so that, in at least one first region of the superficial layer, the electrical field is weaker than in a second region of the superficial layer.Type: GrantFiled: May 27, 2010Date of Patent: April 30, 2013Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventor: Hacène Lahreche
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Patent number: 8283673Abstract: The present invention relates to a crack-free monocrystalline nitride layer having the composition AlxGa1?xN, where 0?x?0.3, and a substrate that is likely to generate tensile stress in the nitride layer. The structure successively includes the substrate; a nucleation layer; a monocrystalline intermediate layer having a selected thickness on the nucleation layer; a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% having a selected thickness on the intermediate layer and a relaxation rate, at ambient temperature, of less than 80%; and the monocrystalline nitride layer.Type: GrantFiled: December 7, 2011Date of Patent: October 9, 2012Assignee: SoitecInventor: Hacene Lahreche
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Patent number: 8253170Abstract: In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).Type: GrantFiled: May 16, 2011Date of Patent: August 28, 2012Assignee: Soitec SA & Soitec USA, Inc.Inventor: Hacène Lahreche
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Patent number: 8198628Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.Type: GrantFiled: March 25, 2008Date of Patent: June 12, 2012Assignee: SoitecInventors: Robert Langer, Hacène Lahreche
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Publication number: 20120074427Abstract: The present invention relates to a crack-free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, and a substrate that is likely to generate tensile stress in the nitride layer. The structure successively includes the substrate; a nucleation layer; a monocrystalline intermediate layer having a selected thickness on the nucleation layer; a monocrystalline seed layer of an AIBN compound in which the boron content is between 0 and 10% having a selected thickness on the intermediate layer and a relaxation rate, at ambient temperature, of less than 80%; and the monocrystalline nitride layer.Type: ApplicationFiled: December 7, 2011Publication date: March 29, 2012Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventor: Hacene Lahreche
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Patent number: 8093077Abstract: The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, on a substrate that is likely to generate tensile stress in the layer and to structures containing such layer and substrate. The method includes forming a nucleation layer on the substrate; forming a monocrystalline intermediate layer of aluminum or gallium nitride at a selected thickness on the nucleation layer; forming a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% at a selected temperature and thickness on the intermediate layer with the thicknesses of the seed and intermediate layers being in a ratio of between 0.05 and 1; and forming the monocrystalline nitride layer of AlxGa1-xN nitride at a selected temperature on the seed layer, with the temperature of formation of the seed layer being 50 to 150° C.Type: GrantFiled: March 11, 2009Date of Patent: January 10, 2012Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Hacene Lahreche
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Publication number: 20110215380Abstract: In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Applicant: S.O.I.TEC Silicon on Insulator TechnologiesInventor: Hacène Lahreche
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Patent number: 7968390Abstract: In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).Type: GrantFiled: September 22, 2009Date of Patent: June 28, 2011Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventor: Hacène Lahreche
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Publication number: 20110012128Abstract: The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, on a substrate that is likely to generate tensile stress in the layer and to structures containing such layer and substrate. The method includes forming a nucleation layer on the substrate; forming a monocrystalline intermediate layer of aluminum or gallium nitride at a selected thickness on the nucleation layer; forming a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% at a selected temperature and thickness on the intermediate layer with the thicknesses of the seed and intermediate layers being in a ratio of between 0.05 and 1; and forming the monocrystalline nitride layer of AlxGa1-xN nitride at a selected temperature on the seed layer, with the temperature of formation of the seed layer being 50 to 150° C.Type: ApplicationFiled: March 11, 2009Publication date: January 20, 2011Inventor: Hacene Lahreche
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Publication number: 20100258846Abstract: The disclosure relates to electronic devices and associated methods of manufacture including materials of the Group III/N. An exemplary device successively includes, from its base towards its surface: (i) a support substrate, (ii) a layer adapted to contain an electron gas, (iii) a barrier layer, and (iv) a superficial layer extending on at least one part of the surface of the barrier layer, wherein the superficial layer has an electrical field of which the current is controlled so that, in at least one first region of the superficial layer, the electrical field is weaker than in a second region of the superficial layer.Type: ApplicationFiled: May 27, 2010Publication date: October 14, 2010Applicant: S.O.I.TEC Silicon on Insulator TechnologiesInventor: Hacéne Lahreche
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Publication number: 20100258898Abstract: An electronic device made of group III/N materials and a method of fabricating the device. The method includes growing by epitaxy on a substrate layer the following successive layers: a layer adapted to contain an electron gas, a barrier layer, and a surface layer. The method also includes an etching step performed on at least part of the surface layer. After the etching step, an epitaxial regrowth is performed to grow a covering layer on the etched surface layer. The material of the surface layer and the material of the covering layer include at least one Group III element and nitrogen.Type: ApplicationFiled: May 26, 2010Publication date: October 14, 2010Applicant: S.O.I TEC Silicon on Insulator TechnologiesInventor: Hacène Lahreche
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Publication number: 20100044705Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.Type: ApplicationFiled: March 25, 2008Publication date: February 25, 2010Inventors: Robert Langer, Hacène Lahreche
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Publication number: 20100038682Abstract: In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).Type: ApplicationFiled: September 22, 2009Publication date: February 18, 2010Inventor: Hacène Lahreche
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Patent number: 7488385Abstract: The invention concerns the preparation of gallium nitride films by epitaxy with reduced defect density levels. It concerns a method for producing a gallium nitride (GaN) film by epitaxial deposition of GaN. The invention is characterized in that it comprises at least a step of epitaxial lateral overgrowth and in that it comprises a step which consists in separating part of the GaN layer from its substrate by embrittlement through direct ion implantation in the GaN substrate. The invention also concerns the films obtainable by said method as well as the optoelectronic and electronic components provided with said gallium nitride films.Type: GrantFiled: May 28, 2003Date of Patent: February 10, 2009Assignee: LumilogInventors: Hacène Lahreche, Gilles Nataf, Bernard Beaumont
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Publication number: 20070164299Abstract: Electronic circuits dedicated to high frequency and high power applications based on gallium nitride (GaN) suffer from reliability problems. The main reason is a non-homogenous distribution of the electronic density in these structures that originates from alloy disorders at the atomic and micrometric scale. This invention provides processes for manufacturing semiconducting structures based on nitrides of Group III elements (Bal, Ga, In)/N which are perfectly ordered along a preferred crystalline axis. To obtain this arrangement, the ternary alloy barrier layer is replaced by a barrier layer composed of alternations of binary alloy barrier layers. The lack of fluctuation in the composition of these structures improves electron transport properties and makes the distribution more uniform.Type: ApplicationFiled: March 12, 2007Publication date: July 19, 2007Inventors: Hacene Lahreche, Philippe Bove
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Publication number: 20060054926Abstract: Piezoelectric semiconductor structures and methods for fabricating the same are described. In an embodiment, the piezoelectric semiconductor structure includes a support substrate, a channel layer arranged on one side of the support substrate, and a barrier layer formed on the channel layer. The barrier layer is made of alternating binary alloy layers of Type III-Type V semiconductor materials.Type: ApplicationFiled: December 3, 2004Publication date: March 16, 2006Inventor: Hacene Lahreche
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Publication number: 20050269671Abstract: A method for producing a support for epitaxy by forming a layer of insulating monocrystalline silicon carbide or insulating monocrystalline gallium nitride in a first substrate of conducting monocrystalline silicon carbide or gallium nitride. The method also includes transfer of the monocrystalline layer of silicon carbide or gallium nitride onto a second substrate formed from a polycrystalline ceramic material having thermal conductivity of 1.5 W.cm?1.K?1 or more. This method enables high performance electronic components to be produced cheaply, in particular for high frequency power applications.Type: ApplicationFiled: August 10, 2004Publication date: December 8, 2005Inventors: Bruce Faure, Hacene Lahreche
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Publication number: 20050217565Abstract: The invention concerns the preparation of gallium nitride films by epitaxy with reduced defect density levels. It concerns a method for producing a gallium nitride (GaN) film by epitaxial deposition of GaN. The invention is characterized in that it comprises at least a step of epitaxial lateral overgrowth and in that it comprises a step which consists in separating part of the GaN layer from its substrate by embrittlement through direct ion implantation in the GaN substrate. The invention also concerns the films obtainable by said method as well as the optoelectronic and electronic components provided with said gallium nitride films.Type: ApplicationFiled: May 28, 2003Publication date: October 6, 2005Inventors: Hacene Lahreche, Gilles Nataf, Bernard Beaumont