Abstract: To provide a plasma display device which implements a peak luminance higher than prior art, reduces the power dissipation, improves the smoothness of gradation display, and conducts clear display suitable especially for TV display. By setting a plurality of APL levels according to the average value of the scene brightness, and by shortening a sustaining pulse period and increasing the number of sustaining pulses of each sub-field in APL levels having small APL, the peak luminance is raised. Further, by making the sustaining pulse period long in APL levels having large APL requiring large discharge light emission power, the light emission efficiency is improved and the maximum power dissipation is reduced. The luminance distribution in the scene when the APL level is small is detected. On the basis of that information, setting of the number of sustaining pulses and the sustaining pulse period is changed in the same APL level.

Abstract: When gradation data of a present frame is corrected in combination with gradation data of a preceding frame for each display pixel, the level of correction is controlled according to a predetermined dispersion pattern corresponding to a matrix of pixels on a plasma display panel. The display pixels where the gradation level varies in the same way are not corrected uniformly, but some are excessively corrected and some are uncorrected such that they are mixed in a two-dimensional pattern. Moving images displayed on the plasma display panel with gradations expressed according to the subfield process for pixels are prevented from suffering false moving image contours.

Abstract: When gradation data of a present frame is corrected in combination with gradation data of a preceding frame for each display pixel, the level of correction is controlled according to a predetermined dispersion pattern corresponding to a matrix of pixels on a plasma display panel. The display pixels where the gradation level varies in the same way are not corrected uniformly, but some are excessively corrected and some are uncorrected such that they are mixed in a two-dimensional pattern. Moving images displayed on the plasma display panel with gradations expressed according to the subfield process for pixels are prevented from suffering false moving image contours.

Abstract: In order to restrict a degradation of image quality due to fake contours of moving images, gray scale is displayed by dividing one field period into sub-fields and combining the sub-fields including a plurality of sub-fields weighted such that a light intensity of a certain one of the plurality of the sub-fields is smaller than two times a light intensity of a lower sub-field adjacent to the certain sub-field and larger than the light intensity of the lower sub-field. Further, a light intensity information code converter circuit responsive to binary numbers expressing weights of light intensities of the plurality of the sub-fields for outputting a light intensity information expressing weights in a range satisfying a condition that a light intensity of a certain one of the plurality of the sub-fields is smaller than two times a light intensity of a lower sub-field adjacent to the certain sub-field and larger than the light intensity of the lower sub-field.

Abstract: The present invention relates to a plasma display panel of the surface discharge type and the AC type. In the plasma display panel of the present invention, scanning pulses are successively applied to a large number of scanning electrodes while data pulses are successively applied to a large number of data electrodes to write wall charge which corresponds to an image into pixels. Then, sustain pulses whose feeding directions are reversed between a first condition and a second condition which occur alternately are fed between the scanning electrodes and sustain electrodes so that discharge occurs at the positions of the pixels in which the wall charge is written to cause a phosphor to emit light to display the image.

Abstract: A resin molded article having a highly expanded undercut shape and a uniform wall thickness distribution is produced with good productivity by forming a parison as an intermediate molded article by injection molding a thermoplastic resin, expanding said parison in open molds prior to blow molding of the parison in the final shape, then closing the molds, and blow molding said parison in the closed molds to form the final shape of the article.

Abstract: An associative memory cell is implemented by a series combination of two electrically erasable and programmable read only memory transistors inserted in a potential line and complementarily driven by two data lines for making one of the two electrically erasable and programmable read only memory transistors conductive depending upon the logic level of a registration data bit, and the two data lines make both of the two electrically erasable and programmable read only memory transistors conductive for storing a don't-care bit, thereby decreasing the occupation area assigned to the associative memory cell without sacrifice of usability in the associative operation.

Abstract: An associative memory device has associative memory cells arranged in matrix and each implemented by a parallel combination of two electrically erasable and programmable non-volatile memory transistors, and a multi-bit data code stored in a row of associative memory cells allows the two electrically erasable and programmable non-volatile memory transistors of each associative memory cell to selectively enter the programmed state so that a multi-bit key code is checked to see whether or not drain current flows through the electrically erasable and programmable non-volatile memory transistors into a source line.

Abstract: A symbol string collating apparatus includes a memory unit, a shift register, a collating unit, and an encoder. The memory unit includes memory circuits arranged in a matrix, stores a series of variable-length reference data with reference to a lower bit position of each column of the memory circuits, and stores specific data not including the reference data in a remaining portion. The shift register has the number of stages equal to the number of rows of the matrix and stores variable-length reference data to be collated which is externally input in series to the shift register in units of symbols. The collating unit collates the reference data stored in the shift register with the reference data stored in each column of the memory unit in units of bits. The encoder generates an output signal when at least a part of the reference data coincides with the reference data as a result of collating by the collating unit.

Abstract: For improvement in processing speed, a high-speed digital signal processor has a feedback loop from a register which stores the calculating result produced by a Signed Digit (SD) arithmetic unit to one of the input ports of the SD arithmetic unit. The SD arithmetic unit executes an arithmetic operation on an input digital signal and the arithmetic result is formed of both signed digit numbers without the need to convert the calculation result represented by an SD number into a binary number.

Abstract: A string comparator is provided for searching the address of a stored string having substantially the same content as that of an input reference string. This comparator comprises a memory including a number of memory cells arranged in a matrix form having a plurality of rows and a plurality of columns. Each string is stored in the memory in such a manner that the row position of each of the memory cells corresponds to the content of a stored string and the column position of each of the memory cells corresponds to the address of the stored string. A row selector is coupled to the memory for selecting one row of the memory cell matrix corresponding to the content of the input reference string to be compared, so that the content of the memory cells belonging to the row selected by the row selector is read out.

Abstract: A content-addressable memory device for searching the address of an input data is disclosed.The content-addressable memory device comprises:memory means including a matrix of memory cells including a plurality of pairs of columns, the row position of each of the memory cells corresponding to the content of the data, the position of each of the pairs of columns corresponding to the address, the first column of each pair of columns being for storing the data at the exact address and the second column of each pair of columns being for storing the data close to the data stored in the first column of the same pair of columns;row selecting means coupled to said memory means and for selecting a row of the memory cell matrix of said memory means corresponding to the input data to be searched.

Abstract: In a Bloch line pair driving device comprising an inductor circuit which has first and second ends and which generates a magnetic field in a predetermined direction to drive each Bloch line pair transversely of the predetermined direction, a first switch is connected to the second end and is put in an on state to gradually increase an electric current flowing from a first voltage source through the inductor circuit in a preselected sense. Gradual growth of the magnetic field results from the gradual increase of the electric current and keeps each Bloch line pair stable at each position. A current path circuit is connected to the second end along with a second voltage source providing a second voltage different from the first voltage, and is put in an active state during an off state of the first switch. The active state of the current path circuit brings about a quick decrease of the magnetic field to propagate each Bloch line pair from each position.