Abstract: An on-chip temperature sensor for generating a digital output signal representing a temperature value includes: a proportional to absolute temperature (PTAT) buffer for alternately generating a first voltage signal representing a first temperature of the PTAT buffer and a second voltage signal representing a second temperature of the PTAT buffer; an analog to digital (A/D) converter, coupled to the PTAT buffer, for converting the first voltage signal to a first digital voltage signal and for converting the second voltage signal to a second digital voltage signal; and a digital output generating block, for receiving the first digital voltage signal and the second digital voltage signal, and comparing a difference between the first digital voltage signal and the second digital voltage signal with a digital voltage reference signal to generate the digital output signal.

Abstract: An on-chip temperature sensor for generating a digital output signal representing a temperature value includes: a proportional to absolute temperature (PTAT) buffer for alternately generating a first voltage signal representing a first temperature of the PTAT buffer and a second voltage signal representing a second temperature of the PTAT buffer; an analog to digital (A/D) converter, coupled to the PTAT buffer, for converting the first voltage signal to a first digital voltage signal and for converting the second voltage signal to a second digital voltage signal; and a digital output generating block, for receiving the first digital voltage signal and the second digital voltage signal, and comparing a difference between the first digital voltage signal and the second digital voltage signal with a digital voltage reference signal to generate the digital output signal.

Abstract: A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the ordinary FD node. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.

Abstract: A pixel circuit includes a front-end circuit, a signal storage circuit, and an output circuit. All of the front-end circuit, the signal storage circuit and the output circuit are coupled to a common floating diffusion (FD) node. The front-end circuit is arranged to generate pixel signals. The signal storage circuit is arranged to store the pixel signals generated by the front-end circuit, wherein when the pixel circuit is selected for performing a read-out operation, the pixel signals stored in the signal storage circuit are pulled up from original voltage levels to other voltage levels higher than the original voltage levels according to a voltage increment applied to a control voltage of the signal storage circuit. When the pixel circuit is selected for performing the read-out operation, the output circuit generates output signals on an output terminal according to voltage levels of the common FD node, respectively.

Abstract: A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.

Abstract: A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the signal storage circuit. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.

Abstract: A pixel circuit is provided. The pixel circuit may comprise a photodiode, a comparator circuit, a capacitor, a first switch circuit, a second switch circuit and a third switch circuit. The photodiode is arranged to accumulate charges in response to incident radiation, to generate a photodiode signal. The comparator circuit is arranged to generate an output signal according to a voltage level of a specific node within the pixel circuit during a read-out phase of the pixel circuit. The capacitor is coupled between a control voltage terminal of the pixel circuit and the specific node, the first switch circuit is coupled between the photodiode and the specific node, the second switch circuit is coupled between the specific node and an output terminal of the pixel circuit, and the third switch circuit is coupled between the output terminal and the comparator circuit.

Abstract: An image sensor is provided, wherein the image sensor includes a pixel array and a timing controller coupled to the pixel array. The pixel array includes a plurality of pixel circuits, and each pixel circuit of pixel circuits includes a photodiode and a storage node. The timing controller includes a logic circuit for generating a plurality of control signals to respectively control operations of the pixel circuits within the pixel array. Respective photodiodes of the pixel circuits are concurrently reset to a first reference level before generating respective photodiode signals of the pixel circuits. Respective storage nodes of the pixel circuits are sequentially reset to a second reference level. The respective photodiode signals of the pixel circuits are concurrently transmitted to the respective storage nodes of the pixel circuits. The respective photodiode signals of the pixel circuits are sequentially read out from the respective storage nodes of the pixel circuits.

Abstract: A pixel circuit includes a front-end circuit, a signal storage circuit, and an output circuit. The signal storage circuit is coupled to the front-end circuit, and the output circuit is coupled to the signal storage circuit. The front-end circuit is arranged to generate pixel signals. The signal storage circuit is arranged to store the pixel signals generated by the front-end circuit, wherein when the pixel circuit is selected for performing a read-out operation, the pixel signals stored in the signal storage circuit are pulled up from original voltage levels to other voltage levels higher than the original voltage levels according to a voltage increment applied to a control voltage. When the pixel circuit is selected for performing the read-out operation, the output circuit generates output signals on an output terminal according to the other voltage levels, respectively.

Abstract: A pixel circuit includes a front-end circuit, a signal storage circuit, and an output circuit. All of the front-end circuit, the signal storage circuit and the output circuit are coupled to a common floating diffusion (FD) node. The front-end circuit is arranged to generate pixel signals. The signal storage circuit is arranged to store the pixel signals generated by the front-end circuit, wherein when the pixel circuit is selected for performing a read-out operation, the pixel signals stored in the signal storage circuit are pulled up from original voltage levels to other voltage levels higher than the original voltage levels according to a voltage increment applied to a control voltage of the signal storage circuit. When the pixel circuit is selected for performing the read-out operation, the output circuit generates output signals on an output terminal according to voltage levels of the common FD node, respectively.

Abstract: A pixel circuit is provided, where the pixel circuit comprises a photodiode, a buffer circuit, a first capacitor, a first switch, a second switch and a third switch. The photodiode is configured to accumulate charges in response to incident radiation, to generate a photodiode signal. The buffer circuit is configured to output at least one read-out signal, wherein an input terminal of the buffer circuit is coupled to a specific node. The first capacitor is coupled between a control voltage terminal of the pixel circuit and the specific node. The first switch is coupled between the photodiode and the specific node. The second switch is coupled between the input terminal of the buffer circuit and an output terminal of the buffer circuit. The third switch is coupled between the output terminal of the buffer circuit and a read-out terminal of the pixel circuit.

Abstract: A pixel circuit is provided. The pixel circuit may comprise a photodiode, a comparator circuit, a capacitor, a first switch circuit, a second switch circuit and a third switch circuit. The photodiode is arranged to accumulate charges in response to incident radiation, to generate a photodiode signal. The comparator circuit is arranged to generate an output signal according to a voltage level of a specific node within the pixel circuit during a read-out phase of the pixel circuit. The capacitor is coupled between a control voltage terminal of the pixel circuit and the specific node, the first switch circuit is coupled between the photodiode and the specific node, the second switch circuit is coupled between the specific node and an output terminal of the pixel circuit, and the third switch circuit is coupled between the output terminal and the comparator circuit.

Abstract: A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the ordinary FD node. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.

Abstract: A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the signal storage circuit. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.

Abstract: A pixel circuit includes a front-end circuit, a signal storage circuit, and an output circuit. The signal storage circuit is coupled to the front-end circuit, and the output circuit is coupled to the signal storage circuit. The front-end circuit is arranged to generate pixel signals. The signal storage circuit is arranged to store the pixel signals generated by the front-end circuit, wherein when the pixel circuit is selected for performing a read-out operation, the pixel signals stored in the signal storage circuit are pulled up from original voltage levels to other voltage levels higher than the original voltage levels according to a voltage increment applied to a control voltage. When the pixel circuit is selected for performing the read-out operation, the output circuit generates output signals on an output terminal according to the other voltage levels, respectively.

Abstract: A digital double-sampling (DDS) circuit includes a comparator with input nodes respectively connected to a ramp voltage and an image output node of a pixel circuit via a capacitor; a reset switch connected between the input nodes for resetting the capacitor; an analog-to-digital converter (ADC) coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase; a subtractor that subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output; and a clamp circuit that generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.

Abstract: An image processing system for an image sensor includes an analog-to-digital conversion (ADC) unit that performs ADC on pixel signals, thereby generating digital pixel signals; a correlated double sampling (CDS) unit that performs CDS on the digital pixel signals; a black level estimation (BLE) unit that generates a negative offset voltage according to dark voltage obtained from CDS performed on estimating optical black pixels (OBPs) of a pixel array, the negative offset voltage being subtracted from the pixel signals before feeding the pixel signals to the ADC unit; and a black level compensation (BLC) unit that performs BLC on active pixels sensors (APSs) and the compensating OBPs of the pixel array.

Abstract: A driving circuit of an image sensor is provided. The driving circuit can include a pixel array where pixel circuits receiving light and converting the received light into an electrical signal are arranged in columns, an analog-to-digital (ADC) block including a plurality of ADC circuits receiving an analog image signal from pixel circuits arranged in the same column and converting the received analog image signal into a digital signal, and an ADC controller outputting a global signal to control each operation of the ADC circuit. The ADC controller can allow the ADC circuits in the ADC block to operate separately according to at least two timings.

Abstract: An image sensor and a row averaging method for an image sensor capable of simultaneously selecting the pixels of the same color in the same column of different rows in a pixel array and performing a signal process, thereby preventing an increase in an area and a decrease in the sensing speed of the pixels in the sub-sampling mode and the binning mode of the image sensor.

Abstract: A passive type image sensor and a method for operating the same. The passive type image sensor includes a photoelectric conversion section configured to receive light and integrate electric charges; a transfer section configured to transmit the integrated electric charges; an output section configured to received integrated electric charges from the transfer section and amplify and output the amplified electric charges; and an electric charge discharging section configured to discharge the electric charges flowing from the photoelectric conversion section to a common node through the transfer section while integrating the electric charge integration in the photoelectric conversion section.