Patents by Inventor Hadi Abdul-Ridha
Hadi Abdul-Ridha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7719041Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.Type: GrantFiled: March 28, 2007Date of Patent: May 18, 2010Assignee: Newport Fab, LLCInventors: Hadi Abdul-Ridha, David Howard
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Patent number: 7709949Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.Type: GrantFiled: April 22, 2005Date of Patent: May 4, 2010Assignee: Newport Fab, LLCInventors: Tinghao F. Wang, Dieter Dornisch, Julia M. Wu, Hadi Abdul-Ridha, David J. Howard
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Publication number: 20090243114Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.Type: ApplicationFiled: April 22, 2005Publication date: October 1, 2009Inventors: Tinghao F. Wang, Dieter Dornisch, Julia M. Wu, Hadi Abdul-Ridha, David J. Howard
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Patent number: 7220639Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.Type: GrantFiled: May 3, 2005Date of Patent: May 22, 2007Assignee: Newport Fab, LLCInventors: Hadi Abdul-Ridha, David Howard
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Publication number: 20060252218Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.Type: ApplicationFiled: May 3, 2005Publication date: November 9, 2006Inventors: Hadi Abdul-Ridha, David Howard
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Patent number: 6919272Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.Type: GrantFiled: February 1, 2003Date of Patent: July 19, 2005Assignee: Newport Fab, LLCInventors: Tinghao F. Wang, Dieter Dornisch, Julia M. Wu, Hadi Abdul-Ridha, David J. Howard
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Patent number: 6836400Abstract: A method for fabrication of ceramic tantalum nitride and improved structures based thereon is disclosed. According to the disclosed method, an ionized metal plasma (“IMP”) tool is used to create a plasma containing tantalum ions where the plasma is sustained by a mixture of nitrogen and argon gases. The percentage of nitrogen partial flow in the mixture of gases is adjusted so as to result in a layer of tantalum nitride with a nitrogen content of at least 30%. With a nitrogen content of at least 30%, the tantalum nitride becomes ceramic. The ceramic tantalum nitride presents a number of advantages. For example, the fabrication of ceramic tantalum nitride can be easily incorporated into fabrication of semiconductor chips using copper as the interconnect metal. Also, ceramic tantalum nitride can be used as an effective etch stop layer.Type: GrantFiled: January 16, 2001Date of Patent: December 28, 2004Assignee: Newport Fab, LLCInventors: Hadi Abdul-Ridha, David T. Young, Maureen R. Brongo
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Publication number: 20040152302Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.Type: ApplicationFiled: February 1, 2003Publication date: August 5, 2004Applicant: Newport Fab, LLC dba Jazz SemiconductorInventors: Tinghao F. Wang, Dieter Dornisch, Julia M. Wu, Hadi Abdul-Ridha, David J. Howard
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Patent number: 6383821Abstract: A process for manufacturing a semiconductor device includes the formation of tungsten contact plugs suitable for very small geometry devices. As part of the process a tungsten barrier layer is deposited into vias and covering the walls of the vias by a process of ionized metal plasma deposition. The tungsten layer deposited in this manner provides a barrier layer, adhesion layer, and nucleation layer for the subsequent chemical vapor deposition of tungsten contact plug material. Together the two layers of tungsten form contact plugs having a low resistance even when used in the fabrication of very small geometry devices.Type: GrantFiled: October 29, 1999Date of Patent: May 7, 2002Assignee: Conexant Systems, Inc.Inventors: David T. Young, Hadi Abdul-Ridha, Shao-Wen Hsia, Maureen R. Brongo
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Publication number: 20010017757Abstract: A method for fabrication of ceramic tantalum nitride and improved structures based thereon is disclosed. According to the disclosed method, an ionized metal plasma (“IMP”) tool is used to create a plasma containing tantalum ions where the plasma is sustained by a mixture of nitrogen and argon gases. The percentage of nitrogen partial flow in the mixture of gases is adjusted so as to result in a layer of tantalum nitride with a nitrogen content of at least 30%. With a nitrogen content of at least 30%, the tantalum nitride becomes ceramic. The ceramic tantalum nitride presents a number of advantages. For example, the fabrication of ceramic tantalum nitride can be easily incorporated into fabrication of semiconductor chips using copper as the interconnect metal. Also, ceramic tantalum nitride can be used as an effective etch stop layer.Type: ApplicationFiled: January 16, 2001Publication date: August 30, 2001Applicant: Conexant Systems, Inc.Inventors: Hadi Abdul-Ridha, David T. Young, Maureen R. Brongo
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Patent number: 6251796Abstract: A method for fabrication of ceramic tantalum nitride and improved structures based thereon is disclosed. According to the disclosed method, an ionized metal plasma (“IMP”) tool is used to create a plasma containing tantalum ions where the plasma is sustained by a mixture of nitrogen and argon gases. The percentage of nitrogen partial flow in the mixture of gases is adjusted so as to result in a layer of tantalum nitride with a nitrogen content of at least 30%. With a nitrogen content of at least 30%, the tantalum nitride becomes ceramic. The ceramic tantalum nitride presents a number of advantages. For example, the fabrication of ceramic tantalum nitride can be easily incorporated into fabrication of semiconductor chips using copper as the interconnect metal. Also, ceramic tantalum nitride can be used as an effective etch stop layer.Type: GrantFiled: February 24, 2000Date of Patent: June 26, 2001Assignee: Conexant Systems, Inc.Inventors: Hadi Abdul-Ridha, David T. Young, Maureen R. Brongo