Abstract: Described are methods, devices and applications for learning noise distribution on information from any data processing method. In an embodiment of the described technology, a method includes determining an amount of shredding used in a shredding operation by which source data is converted into shredded data, and transferring the shredded data over an external network to a remote server for a data processing task. The shredding reduces the information content and incurs a limited degradation to an accuracy of the data processing task due to the shredding operation.

Abstract: Methods and systems that provide data privacy for implementing a neural network-based inference are described. A method includes injecting stochasticity into the data to produce perturbed data, wherein the injected stochasticity satisfies an ?-differential privacy criterion and transmitting the perturbed data to a neural network or to a partition of the neural network for inference.

Abstract: Provided is a process including: obtaining, with a computer system, a data set having labeled members with labels designating corresponding members as belonging to corresponding classes; training, with the computer system, a machine learning model having deterministic layers and a parallel set of conditional layers each corresponding to a different class among the corresponding classes, wherein training includes adjusting parameters of the machine learning model according to an objective function that is differentiable; and storing, with the computer system, the trained machine learning model in memory.

Abstract: Provided are unsupervised mechanisms for generating obfuscation of data for machine learning applications.

Abstract: Methods, apparatus and systems that relate to hardware accelerators of artificial neural network (ANN) performance that significantly reduce the energy and area costs associated with performing vector dot-product operations in the ANN training and inference tasks. Specifically, the methods, apparatus and systems reduce the cost of bit-level flexibility stemming from aggregation logic by amortizing related costs across vector elements and reducing complexity of the cooperating narrower bitwidth units.

Abstract: A method for database management that includes receiving an algorithm from a user. Based on the algorithm, a hierarchical dataflow graph (hDFG) may be generated. The method may further include generating an architecture for a chip based on the hDFG. The architecture for a chip may retrieve a data table from a database. The data table may be associated with the architecture for a chip. Finally, the algorithm may be executed against the data table, such that an action included in the algorithm is performed.

Abstract: Provided is a system, comprising: a computing device, comprising: computational storage or computational memory, the computational storage or computational memory having a processor; a downstream data processor that is different from the processor of the computational storage or computational memory; and a bus connecting the processor to the computational storage or computational memory, wherein the computing device comprises a tangible, non-transitory, machine readable medium storing instructions that, when executed, effectuate operations comprising: receiving an input from a remote device conveyed to the computing device; determining, based on the input, how to configure a transformation of data stored in the computational storage or computational memory; and applying, with the processor, the configured transformation to the data stored in the computational storage or computational memory; and outputting the transformed data to the downstream data processor.

Abstract: A method for database management is disclosed. The method may include receiving an algorithm from a user. Based on the algorithm, a hierarchical dataflow graph (hDFG) may be generated. The method may further include generating an architecture for a chip based on the hDFG. The architecture for a chip may retrieve a data table from a database. The data table may be associated with the architecture for a chip. Finally, the algorithm may be executed against the data table, such that an action included in the algorithm is performed.

Abstract: Disclosed are devices, systems and methods for accelerating vector-based computation. In one example aspect, an accelerator apparatus includes a plurality of mixed-signal units, each of which includes a first digital-to-analog convertor configured to convert a subset of digital-domain bits to a first analog-domain signal and a second digital-to-analog convertor configured to convert a subset of digital-domain bits to a second analog-domain signal. Each mixed-signal unit also includes a capacitor coupled to the digital-to-analog convertors to accumulate a result of a multiplication operation as an analog signal. The apparatus includes a circuitry coupled to the mixed-signal units to shift part of the analog signals of the plurality of mixed-signal units. The circuitry comprises an additional capacitor to store an analog-domain result for a multiply-accumulate operation.

Abstract: Methods and systems that provide data privacy for implementing a neural network-based inference are described. A method includes injecting stochasticity into the data to produce perturbed data, wherein the injected stochasticity satisfies an F-differential privacy criterion and transmitting the perturbed data to a neural network or to a partition of the neural network for inference.

Abstract: Provided is a process including: obtaining, with a computer system, with a stochastic layer of a multi-layer neural network, inputs to the stochastic layer from, wherein the multi-layer neural network comprises both deterministic layers and the stochastic layer, and the stochastic layer comprises a plurality of parameters that vary stochastically according to respective probability distributions; determining values of the plurality of parameters by randomly sampling from the statistical distributions; determining an output of the stochastic layer based on both the determined values of the plurality of parameters and the inputs to the stochastic layer; and providing the output of the stochastic layer to a downstream layer of the multi-layer neural network or as an output of the multi-layer neural network.

Abstract: Methods and systems that provide data privacy for implementing a neural network-based inference are described. A method includes injecting stochasticity into the data to produce perturbed data, wherein the injected stochasticity satisfies an ?-differential privacy criterion and transmitting the perturbed data to a neural network or to a partition of the neural network for inference.

Abstract: Methods and systems that provide data privacy for implementing a neural network-based inference are described. A method includes injecting stochasticity into the data to produce perturbed data, wherein the injected stochasticity satisfies an ?-differential privacy criterion and transmitting the perturbed data to a neural network or to a partition of the neural network for inference.

Abstract: Methods and systems that provide data privacy for implementing a neural network-based inference are described. A method includes injecting stochasticity into the data to produce perturbed data, wherein the injected stochasticity satisfies an ?-differential privacy criterion and transmitting the perturbed data to a neural network or to a partition of the neural network for inference.

Abstract: A random access memory may include memory banks and arithmetic approximation units. Each arithmetic approximation unit may be dedicated to one or more of the memory banks and include a respective multiply-and-accumulate unit and a respective lookup-table unit. The respective multiply-and-accumulate unit is configured to iteratively perform shift and add operations with two inputs and to provide a result of the shift and add operations to the respective lookup-table unit. The result approximates or is a product of the two inputs. The respective lookup-table unit is configured produce an output by applying a pre-defined function to the result. The arithmetic approximation units are configured for parallel operation. The random access memory may also include a memory controller configured to receive instructions, from a processor, regarding locations within the memory banks from which to obtain the two inputs and in which to write the output.

Abstract: A method for database management is disclosed. The method may include receiving an algorithm from a user. Based on the algorithm, a hierarchical dataflow graph (hDFG) may be generated. The method may further include generating an architecture for a chip based on the hDFG. The architecture for a chip may retrieve a data table from a database. The data table may be associated with the architecture for a chip. Finally, the algorithm may be executed against the data table, such that an action included in the algorithm is performed.

Abstract: Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence predicates, while minimizing the communication between the cores.

Abstract: Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence predicates, while minimizing the communication between the cores.